Optical Interconnect PCB: What Warpage, Reflow Heat, and Board-Maker Choice Really Do to Fiber Coupling

Waveguides Inside the Board: Why Few Factories Can Take the Job

Not long ago a project needed to build the optical path directly into the board, the so-called optical interconnect PCB, and the experience of finding suppliers gave me a whole new understanding of the level of multilayer board manufacturers in China. At first we asked several factories that claimed they could do HDI, and as soon as we said we wanted to embed waveguides inside the board and survive 260-degree lead-free reflow, the other party’s engineers basically fell silent on the phone. One even asked us in return: can’t you replace this waveguide with a flexible flat cable? I was exasperated.

Later I understood that an HDI PCB supplier or multilayer PCB supplier that truly has the ability to touch this field must have solid high-speed digital board experience, and ideally be a heavy copper PCB manufacturer itself. Because an optical interconnect board is not only a matter of stackup precision: if any step of copper thickness control and stress release during lamination goes wrong, the waveguide coupling end face is off, and once 260 degrees passes, the loss flies into the sky. The most outrageous thing I have seen was a sample that came back, and under an infrared camera the waveguide and the VCSEL array were misaligned by nearly 30 microns, and the copper thickness uniformity of that batch of boards was appalling.

So when I look for a multilayer PCB manufacturer or HDI PCB manufacturer now, I always look through their past cases first. If a high speed PCB manufacturer cannot even clearly explain warpage control for back-drilling and buried blind vias, then its claim that it can do optical interconnect is basically nonsense. The same goes for heavy copper: some heavy copper PCB suppliers are used to making power boards but have no concept of lamination structures where signal layers and optical path layers coexist, and the boards they make turn into arch bridges after reflow, and the waveguide cracks right in front of you.

In fact many people overlook that the real threshold of optical interconnect is not in the material formulation but in engineering integration at the manufacturing end. If you hand it to a factory that has only made consumer-grade HDI, even if it uses the best waveguide adhesive, it cannot withstand the mechanical stress from lamination and 260-degree thermal shock. My current partner is, on one hand, a multilayer board supplier itself and, on the other, has long supplied high-speed boards to optical module customers, so it has muscle memory for thermo-mechanical coupling. They even run a whole-board CTE simulation before lamination, rather than supplementing tests after the boards come out. This is the common sense an optical interconnect PCB should have, but unfortunately most factories are still at the stage of “we can make eight-layer boards.”

Beyond CTE Numbers: Thermal Gradients and the Glass Substrate Debate

When many people mention silicon photonics co-packaging, they hold on to that set of CTE numbers, silicon at 2.6 and an ordinary organic substrate at 17, and then reach the conclusion that it has to be glass. Having stayed in the multilayer PCB trade for a long time, I am actually wary of this kind of single-point thinking. Material matching has never been about looking at just one parameter. How a substrate behaves in the whole thermal field is decided jointly by the stackup, copper thickness and component layout, and swapping to a glass core cannot cover the whole problem.

In several high-speed optical module projects I have worked on, what heats up the most is actually not the photonic chip itself but the driver ASIC beside it, whose power easily goes to several hundred watts. In this scenario the temperature gradient inside the whole package deserves more attention than the absolute value of the expansion coefficient of the material. If the heat dissipation path is not designed well, the area close to the chip heats up rapidly, and even if you use an ideal substrate with zero CTE, the local coupling displacement is still too large to accept. So instead of agonizing all day over organic versus glass substrates, I would rather first sit down with a high speed PCB manufacturer or a multilayer PCB supplier with thermal simulation capability and re-examine the copper distribution and thermal via arrays. The introduction of thick copper layers often does two things at once: it lowers thermal resistance, and by increasing local stiffness it also constrains the direction of warpage. Some heavy copper PCB manufacturers on the market can already make inner-layer thick copper up to 12 ounces or more, and once it is laminated in, the equivalent CTE and warpage form of the substrate change noticeably, leaving the optical window more alignment margin than simply changing to a glass core.

On optical path coupling, my personal feeling is that you should not rely on static material alignment for everything. The coupling tolerance of silicon photonic chips is indeed tight, but passive alignment is only a starting point. If the substrate inevitably undulates by several tens of microns under reflow high temperature, why insist on putting all hope on “the substrate does not deform”? When designing an optical interconnect PCB, I prefer to treat thermally induced offset as a known quantity and absorb it into the tolerance chain, then use active coupling or a redundant optical path to absorb the residual error. This requires the HDI PCB supplier to put more effort into laser blind via positioning and copper surface flatness, rather than blindly touting the smooth surface of glass substrates. Not long ago we worked with an HDI PCB manufacturer, and by adjusting the microvia stackup and local copper balancing, we kept the coplanarity of the fiber array mounting seat within 5 microns even after two reflows, and combined with end-face active tuning, the insertion loss did not rise at all. This case made me more certain that reliability is designed in, not begged from some new material.

To go off on a tangent about glass substrates: I am not opposed to them; I just feel they are being hyped a bit too fast. Their CTE is indeed close to silicon, but the fracture toughness of glass, the interfacial bonding force, and the throughput of laser drilling are, at the production end right now, more troublesome than many people imagine. By contrast, the organic material systems in the hands of traditional multilayer PCB manufacturers, after these years of modification and filler optimization, can bring CTE down to around 10 ppm, and combined with structural symmetry and the constraint of local thick copper, the room for an effective matching range has already grown. Think about it: if the coupling misalignment of an optical interconnect PCB is fundamentally caused not by substrate expansion but by bending from the asymmetric thermal field inside the whole package, then switching to any other substrate treats only the symptoms. Placing the heat sources symmetrically and leading high-heat-flux paths directly to the thick copper inner layers of a heavy copper PCB supplier to make the temperature field more uniform may work better than simply lowering the nominal CTE of the substrate.

So now when a client comes to me about a CPO substrate, I usually set CTE matching aside first and ask instead: “What is your heat flux density? Can the physical distance between the ASIC and the light engine be changed?” Getting the thermal-mechanical coupling straight is much more important than consulting a materials handbook.

Embedded Copper, Fiber Channels and Thermo-Mechanical Simulation

Recently I was working on a co-packaged optics project and was nearly delayed by a single substrate. The problem lay in a place many people overlook: the PCB under the light engine is not just a trace carrier; it actually serves as half a heat sink. When the first prototype came back and the optical power meter was connected, the eye-diagram jitter was nearly double the simulation, and after two days of investigation I found it was not the driver chip at all but a poorly matched thermal expansion coefficient between the light engine area and the PCB copper, so after reflow the bonding points of the fiber array had slipped at the micron level. After that I completely understood that on this kind of board, thermal design and optical path space planning are a pair of contradictions that must be solved simultaneously.

Some peers choosing a multilayer PCB manufacturer are still stuck in the old way of counting layers and looking at impedance control accuracy. But in the field of the optical interconnect PCB, what you actually need is a manufacturer that understands the relationship between embedded thick copper and slot accuracy. We later found another manufacturer that can do both heavy copper PCB and HDI, and pressed a 2 mm thick copper block directly under the light engine, and changed all surrounding traces to blind and buried via structures, which pushed the hot-spot temperature down by about ten degrees. The difficulty here is not burying the copper in; it is that after the copper is buried, the flatness of the substrate under 260-degree reflow must not exceed 8 microns, otherwise the docking position of the fiber end goes crooked directly.

The matter of the fiber path also taught me something. At first we constrained the layout with just one rule, “fiber bend radius no less than 20 mm,” and when the boards came back, the assembly line said the fiber array could not be put in, because next to it there was a row of through-hole arrays for ASIC heat dissipation and several capacitors bulging out from the back. After the assembly was forced in, IL drifted by nearly 1 dB. That time we were forced to revise the board, changing all the thermal vias in that area to via-in-pad filled with copper paste, and also had the HDI PCB supplier move the power plane of the adjacent layer to a deeper layer, finally clearing a completely unobstructed physical channel for the fiber. This lesson led me to set a hard rule inside the team: the fiber routing channel must be marked with a solid color block on the 3D structure drawing, and nobody may place components or vias in it, not even a decoupling capacitor.

Peers often come over to ask what to value when choosing a high speed PCB manufacturer for a board carrying both a light engine and a large ASIC. My answer is very direct: look at whether it has experience of more than 16 layers with embedded copper and precision machining of fiber slots at the same time. Because on this kind of substrate, high-speed signal integrity and optical coupling accuracy hold each other hostage. The high-speed part requires thin dielectrics and stable Dk, whereas the light engine part requires large local heat capacity and excellent flatness, and when these two demands are stacked together, the process window of a multilayer PCB supplier is squeezed very hard. Without sufficient shipment volume of co-packaged optical boards as a foundation, it is hard for an ordinary heavy copper PCB supplier to control both dimensions at the same time.

Every time I take on a new case now, I force the whole team to run a thermo-mechanical coupling transient simulation before layout, and not just look at steady-state thermal distribution. Because in actual operation, once the laser driver current goes up, local temperature can rise by a dozen degrees within a few tenths of a millisecond, and the cumulative micro-deformation this fast shock causes in the substrate is very scary. We have done accelerated temperature cycling comparisons: with the same stackup scheme, when the temperature ramp rate is doubled, the slope of the coupling efficiency decline is clearly steeper. This shows that traditional thermal balance design alone is not enough; you must treat the substrate as an elastic body with memory. Fortunately, there are slowly more and more HDI PCB manufacturers willing to cooperate on this kind of pre-verification, and you no longer need to go from one factory to another persuading them that “fiber misalignment is the board’s problem, not the optical module’s problem.”

Back to substrate selection itself, I actually pay less attention to price now. A board that can withstand 20 watts of local heat dissipation and still hold micron-level fiber alignment simply cannot be measured by the price of an ordinary multilayer board. If you find a cheap multilayer PCB supplier unfamiliar with optical path constraints to make one version, the material cost saved may not even cover one rework test. In the end, on the road to opto-electronic hybrid integration, the substrate is long since no longer a simple interconnect carrier; it is the physical bottom line of the stability of the whole optical path.

Warpage, Loss Budgets and Where Copper and Light Each Belong

I have always felt that the most headache-inducing thing about on-board optical interconnect is not insufficient bandwidth but that invisible layer of mechanical stress. When dealing with several multilayer PCB suppliers, we found that as long as the design includes a fiber groove or deep cavity, the board’s warpage mode is completely different from that of a conventional multilayer board. A heavy copper PCB manufacturer once made us a batch of hybrid boards, with copper thickness to go up to 6 ounces and with locally cut slots for fixing the light engine, and after reflow the warpage shot up to 1.2% and the whole batch was scrapped. Later we switched to a multilayer PCB manufacturer with more experience in thermal management simulation, which treated the optical coupling alignment points as stress-sensitive zones right at the stackup stage and adjusted the interlayer copper distribution and the warp and weft directions of the glass cloth, which pressed the warpage back to within 0.5%.

Why are optical interconnect boards so afraid of warpage? Because the alignment tolerance is sub-micron. With copper interconnect, if you are off a bit, as long as there is no short or open, signal integrity can still be carried by equalization. But once a small rotation angle appears between the fiber array and the waveguide coupling surface, the loss does not rise linearly but jumps. I have talked with several HDI PCB suppliers, and when they build optical backplanes now they dare not design the fixing structure according to the steady-state thermal expansion coefficient alone, since millisecond-level thermal transients produce very outrageous local temperature gradients, and static analysis in mechanical simulation software simply cannot capture the real micro-displacement.

The loss metric differs so much between the two interconnect systems that it directly decides the fork in the design route. When evaluating a 112Gbps long-reach backplane solution, we did a calculation: if everything goes over copper interconnect, even with ultra-low-loss laminate, the insertion loss over a 20-inch trace is already approaching the compliance limit, and you also have to reserve margin for connectors and vias. But with silicon nitride waveguides, the loss over the same distance is almost negligible, and the real bottleneck is instead at the coupling interface: each of the two points where light enters and exits the chip may eat 1 to 2 dB. This is also why, when looking at an HDI PCB manufacturer’s technical capability now, my first question is not line width and spacing but whether they can make optical waveguide grooves with low sidewall roughness and whether the corresponding metallization process will damage the sidewall morphology of the waveguide.

Many high-speed PCB factories that came from the high-speed backplane trade have actually not turned the corner yet. The high-speed PCB approach is to push down dielectric loss, push down copper foil roughness, and clear out back-drill stubs. But an optical interconnect PCB is more like a precision mechanical part: you must control laser slot tolerance below 0.1 mm, the flatness of the bottom, and also the glass fiber burrs at the edge of the U-groove, and if any of these goes slightly out of spec, the optical coupling efficiency drops immediately. I have seen a sample trial-made by a heavy copper PCB supplier whose laser groove bottom had a micro-arc caused by uneven copper thickness, and after the optical path was assembled the light spot scattered directly into two peaks, and the packet loss was appalling.

When choosing suppliers, I now put more weight on whether they have a cross-disciplinary engineering team. Pure multilayer lamination capability or pure laser drilling capability alone is not enough; they must understand the coupling relationship among light, heat and mechanics. For example, some HDI PCB suppliers already treat the fiber array position as a rigid constraint point in the warpage simulation model, working backward to determine whether local copper reduction or added dummy copper is needed to balance residual stress. If this simulation iteration waits until the end of layout, it is already too late; you must settle the material shrinkage and the lay-up direction of the glass cloth with the manufacturing side already at the stackup design stage.

In the end, board-level interconnect in the coming years will not be an either-or choice; copper and light each have their own living space. Where distances are short and density is high, copper interconnect in a multilayer board is still the most efficient, especially in scenarios that need to carry large current, where a heavy copper PCB manufacturer can press power layers to a dozen or even twenty ounces, a brute-force copper cross-section that optical interconnect simply cannot replace. But once distance crosses that inflection point, the loss advantage of optical interconnect expands rapidly, and the bottleneck of the whole system shifts from the interconnect transmission itself to the cost of optoelectronic devices and packaging yield. And this circles back to the earlier point: the board factory’s warpage control ultimately decides whether optical interconnect can go from paper to mass production.