{"id":10539,"date":"2026-08-25T15:01:00","date_gmt":"2026-08-25T07:01:00","guid":{"rendered":"https:\/\/www.sprintpcbgroup.com\/?p=10539"},"modified":"2026-08-25T11:52:23","modified_gmt":"2026-08-25T03:52:23","slug":"central-unit-pcb-odu-multilayer-manufacturer-signal-integrity","status":"publish","type":"post","link":"https:\/\/www.sprintpcbgroup.com\/ja\/blogs\/central-unit-pcb-odu-multilayer-manufacturer-signal-integrity\/","title":{"rendered":"Central Unit PCB for O-DU: Why the Board Manufacturer Decides More Than FPGA vs ASIC Ever Will"},"content":{"rendered":"
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Why the Multilayer Board Manufacturer Decides More Than FPGA vs ASIC<\/p>

In my early years building communication equipment, I always believed a board’s soul was the main chip on it \u2014 FPGA or ASIC, how much compute power, how many channels it could run. It was only after digging deep into O-DU projects that I gradually came around: what a Central Unit PCB<\/a> genuinely needs to survive real-world field conditions has far less to do with which chip you chose, and far more to do with whether the multilayer PCB manufacturer you signed with is actually reliable.<\/p>

The DU’s physical-layer processing demands are brutally strict on timing and signal integrity \u2014 a single DDR4 trace slightly mishandled, or an impedance deviation baked into the board’s layer stack-up, and your carefully assembled hardware acceleration architecture takes an immediate discount. I once saw a team use an extremely expensive FPGA, only to have uneven resin flow during PCB lamination push transmission-line insertion loss straight past spec, sending the fronthaul interface’s eCPRI packet loss rate through the roof \u2014 it took two months of investigation to find the problem was never the chip, it was the multilayer board itself. They later switched to a multilayer PCB supplier who had built high-speed backplanes for military applications \u2014 with essentially the same FPGA design and almost no BOM changes, the Unit’s overall performance stabilized immediately.<\/p>

So now, if someone asks me how to approach DU chip selection, I turn it around and ask them first: who’s building your PCB? All those discussions endlessly debating NVIDIA Aerial versus Xilinx Versal actually skip right past the most fundamental layer. In high-end multilayer boards, copper foil roughness, dielectric thickness consistency, and back-drill stub residual length are the real hands pulling the Unit’s noise floor and latency numbers back down from paper specs to reality. You might save power by choosing an ASIC-integrated solution, but if the board shop’s process is not up to par, signal crosstalk alone can eat away half your link budget \u2014 and that power-saving advantage isn’t worth much against the cost of retransmissions from transmission errors.<\/p>

My own habit is: at the start of a DU project, spend two or three weeks talking with the multilayer PCB manufacturer’s process engineers, looking at their high-frequency board<\/a> material inventory and processing capability, even taking a cross-section of a board for metallurgical analysis. Only once I have that confidence do I go back and finalize the chip architecture. This sounds backwards, but a Central Unit PCB that can stably run at its full designed performance is often more valuable than piling on an extra 10% compute power in the chip. At the end of the day, the Unit sits in a rack, out in the wind and sun doing real work \u2014 it’s not something running benchmarks in a lab.<\/p>

Working in hardware for these years, I have increasingly come to feel that a board’s soul isn’t in the main chip \u2014 it’s circulating in the signal traces winding through dozens of layers of copper foil. Not long ago, a project needed to build an O-DU processing unit for an outdoor small cell. The client insisted on using a high-compute GPU to run physical-layer algorithms. We spent a full two weeks evaluating this and found that simply fitting the GPU’s memory bus and fronthaul interface into a Central Unit PCB that could fit inside a 19-inch rack enclosure was already headache-inducing enough \u2014 not to mention the whole thermal-dissipation mess on top of that.<\/p>

Many people think choosing FPGA versus GPU is purely a matter of compute power \u2014 it’s not that at all. You first have to ask yourself whether the multilayer PCB manufacturer in your hands can stably build the layer stack-up you need. Take that central unit, for example \u2014 we needed to simultaneously carry 100Gbps-class fronthaul data streams while leaving a low-latency path for beamforming. Going with traditional FR4 material on a sixteen-layer board, signal attenuation could close the eye diagram down to a sliver. We later switched to a multilayer PCB supplier specializing in high-speed backplanes, who recommended M6-grade copper-clad laminate with a twenty-layer any-layer interconnect process, which barely brought insertion loss within budget. At that point, look back at chip selection \u2014 if you had originally chosen a flagship GPU with power dissipation spiking to two hundred watts, just the power plane group needed to feed its core would eat up a full four layers of copper, leaving nowhere near enough room for logic routing. After all that struggle, a mid-scale FPGA turns out to be far cleaner.<\/p>

On the subject of power consumption, many architects only look at the TDP number in a chip datasheet, forgetting that the board-level power distribution network itself will also eat away ten-plus percent of efficiency loss. Especially when you pile on a bunch of tantalum capacitors and multi-phase controllers to accommodate a GPU’s large-current transient response, the entire Central Unit PCB’s thermal density becomes extremely uneven. Last winter I measured a prototype board where the corner temperature was only in the low forties, while the region directly under the FPGA had a local hotspot approaching one hundred and five degrees. We eventually had to re-plan the air channel and even drilled over twenty thermal-conduction holes in the backplane just to barely pass. This is exactly when you understand why manufacturers who have actually delivered products at volume would rather sacrifice a bit of peak compute power to keep whole-board power dissipation under one hundred and twenty watts \u2014 because past that threshold, even finding a reliable outdoor cabinet thermal solution becomes a struggle.<\/p>

There’s another common misconception \u2014 thinking that using a heterogeneous SoC lets you have your cake and eat it too. In reality, the bandwidth bottleneck between the SoC’s hardened processor and the programmable logic gets overlooked far too often. I once ran downlink processing on a 16nm SoC from one vendor, and simply moving the FFT result from the ARM core to the accelerator on the logic side added nearly three microseconds of extra delay. That delay looks harmless in a lab, but the moment you hit multi-user scheduling in the field, the fronthaul window gets crushed immediately. We eventually had no choice but to hang a lightweight soft core on the logic side dedicated purely to data movement \u2014 essentially trading area for time. Whether that trade is worthwhile depends entirely on how strict your real-time requirements really are.<\/p>

Looking back, I’d actually argue that instead of agonizing over FPGA versus GPU from the start, you’re better off spending your energy on the capability boundary of your multilayer PCB supplier \u2014 ask them how fine a trace width and spacing they can achieve, whether they support back-drilling, and whether they’ve built similar RF mixed-signal boards<\/a> before. Because no matter which main chip you eventually choose, all your ideas ultimately have to be realized through that stack of copper-clad laminate and prepreg. And good board shops today routinely quote lead times of eight weeks or more \u2014 if you haven’t aligned with them early, changing the stack-up once later on will throw the entire project schedule into chaos. None of these pitfalls can be sidestepped just by reading a few datasheets \u2014 you only really learn the lesson after paying real tuition.<\/p>\t\t\t\t\t\t\t\t<\/div>\n\t\t\t\t

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I’ve done several DU projects, and every single time the biggest headache was never which chip to choose \u2014 it was how to get that Central Unit PCB to hold its ground between performance and cost. Too many people jump straight into debating FPGA versus ASIC, as if selection were a simple either-or choice, but they rarely mention the real pain of actual deployment. Take a small-cell project we did last year, for example \u2014 using an ASIC baseband chip genuinely lowers power consumption and makes board-level thermal design easier, but the problem is that when you need to adapt to non-standard fronthaul interfaces or support different vendors’ RRUs, that ASIC’s fixed pipeline becomes absolutely maddening. We eventually just redesigned the board with a small-capacity FPGA handling interface adaptation, hanging an ASIC afterward for channel processing \u2014 the whole DU’s PCB layer count was slashed from twenty layers down to fourteen, and finding a reliable multilayer PCB manufacturer<\/a> became critical at that point. Not every multilayer board shop can handle this kind of mixed-signal routing and back-drilling process \u2014 we went through three suppliers before finding one that could stably control FR4 dielectric loss. I’ve since found that as long as you align impedance control and copper foil roughness details with your multilayer PCB supplier’s engineering team ahead of time, many so-called “signal integrity difficulties” don’t require piling on expensive board material at all. At the end of the day, DU is inherently cost-sensitive going forward \u2014 ASIC saves power but lacks flexibility, FPGA is flexible but expensive and hot, and the real balance point actually lands on PCB process and supply-chain coordination. Stop staring only at parameters in a chip datasheet \u2014 go down and have a meal with the people at the board shop, and you might come away with a completely different understanding of Central Unit PCB design.<\/p>

Many people, when discussing O-DU, habitually pour all their attention into baseband chips or protocol-stack software, but I think what genuinely determines whether a DU device can run stably is that Central Unit PCB. If the board is not well designed, no matter how strong your compute power, it’s all wasted. I once participated in a project where, to rush the schedule early on, we casually found a multilayer PCB manufacturer \u2014 the prototype came back and tested against fronthaul, and the 25Gbps eCPRI link’s bit error rate simply would not come down, packet loss was severe enough that RRUs kept dropping. It was only after investigation that we discovered this shop had zero experience with high-speed board material \u2014 the stack-up was a mess, SerDes traces were routed carelessly, and impedance control was nowhere near tolerance. We later resolutely switched to a multilayer PCB supplier who genuinely understood communication boards, redid the stack-up simulation, sandwiching critical signal layers between two complete reference planes, and switched to low-loss material \u2014 that single change alone raised the fronthaul link’s eye-diagram margin from essentially zero to comfortable headroom.<\/p>

The pitfalls on the fronthaul side don’t stop at signal integrity. Many people think fronthaul bandwidth is just a theoretical calculation \u2014 leaving 25Gbps of headroom is enough \u2014 but real-world networks get complex quickly, for instance needing to support cascading or ring-network protection, and bandwidth requirements can immediately double. And the DU’s MAC-layer scheduling is extremely sensitive to latency jitter \u2014 we measured that if jitter introduced by the fronthaul switch or PCB routing exceeds two or three microseconds, HARQ feedback can time out, directly affecting user experience. So we later directly reserved multiple 25GbE ports on the Central Unit PCB, even starting to consider evolving to 50GbE, and built dual-mode redundancy for 1588v2 and SyncE synchronization \u2014 all of this had to be locked in at the board-design stage; there’s no changing it afterward.<\/p>

Power consumption is another easily underestimated pain point. I often hear people apply data-center thinking to DU, thinking a single-board power dissipation of two or three hundred watts is no big deal, but edge equipment rooms and outdoor cabinets have completely different cooling conditions. We ran a comparison \u2014 two Central Unit PCBs with similar functionality, differing only in power architecture and PCB copper thickness design, could differ in full-load power consumption by 40 watts \u2014 in a sealed outdoor environment, that directly determines whether the equipment survives the summer. Our current design principle locks the power budget under 150 watts from the very start; anything exceeding that line requires optimization even at the cost of some processing capability \u2014 for instance, moving parts of the pipeline that don’t need real-time processing to an auxiliary card, or shaving peaks through dynamic frequency scaling. Waiting until after you’ve selected your multilayer PCB supplier and the board is already finalized to think about these things is basically too late.<\/p>

Working in hardware for these years, I’ve increasingly come to feel that a lot of people think about FPGA accelerator cards too narrowly. The moment selection comes up, all eyes go straight to the main chip’s model, LUT resources, DSP count \u2014 as if strong enough compute power means you just plug it into a server and everything’s settled. But what actually tripped me up was that unremarkable Central Unit PCB. The board’s own design, stack-up, material, even the board shop’s process control, often directly determines whether an accelerator card can run stably in the chassis for two years.<\/p>

I had a project where we selected an FPGA accelerator card that, upon evaluation, was extremely well-suited \u2014 Verilog code simulated fine, and it tested normally for the first three days on the board. Then, starting on the seventh day, the server intermittently reported PCIe training failures, with the link downshifting. We initially suspected the driver, and after two weeks of struggling, finally used a TDR to find the problem was in those few vias on the PCB traces \u2014 signal integrity margin was insufficient, and impedance control on the high-speed differential pair was off. Taking it apart for comparison afterward, we discovered this multilayer PCB manufacturer used ordinary FR-4 material, with a stack-up structure that hadn’t been optimized for signals above 16Gbps \u2014 but our accelerator card was running PCIe Gen4, already pushing against the ceiling of the material. This wasn’t the FPGA’s fault \u2014 it was the carrier itself that couldn’t hold up.<\/p>

For future selection, I started paying particularly close attention to the accelerator card manufacturer’s supply-chain foundation. A good multilayer PCB supplier can use Panasonic MEGTRON or Taiyao TU-872 type low-loss board material, with completely different routing rules and back-drilling processes. This has nothing to do with FPGA, but it directly relates to whether your accelerator card can survive a three-year lifecycle inside a server. Especially now, as internal server temperatures climb and cooling becomes more uneven, if a PCB’s thermal expansion and contraction isn’t well controlled, BGA solder joints on the board can develop micro-cracks \u2014 the resulting fault symptoms are extremely erratic, intermittent, maddening to troubleshoot.<\/p>

There’s another layer \u2014 production capacity and delivery stability. We got burned before: an FPGA accelerator card used a custom stack-up from a particular PCB supplier, and that shop’s capacity got tight, delaying our order by a full nine weeks. The entire server sat waiting for the accelerator card, and the whole project schedule was stuck. The team reflected afterward that even though the FPGA chip itself had multiple sourcing options, once the PCB was tightly bound to a specific supplier’s process, the risk of supply cutoff was just as significant as the chip’s. Now I require partners to provide at least two certified multilayer PCB suppliers \u2014 even if switching costs run a bit higher, that beats being held hostage by a single supplier.<\/p>

Many people, when discussing ecosystems, always think it’s about drivers, toolchains, SDKs \u2014 software-layer things \u2014 but I think the genuine hardware ecosystem has to be counted starting from this Central Unit PCB’s supply chain. Whether your board design can easily be produced across multiple board shops, whether you’re forced into using one shop’s unique process \u2014 these are all part of continuous delivery capability. An FPGA accelerator card ultimately has to plug into a server and get to work \u2014 it’s not meant to sit in a lab running a demo and calling it done. Software can iterate, drivers can update, but once a board with a design flaw is deployed at volume, recalling it is a disaster-level cost.<\/p>

Working in hardware for a long time, what I fear most is that lose-lose situation. Last year, a project needed to build a Central Unit PCB hanging inside an O-RAN distributed unit, requiring fronthaul processing and partial baseband computation crammed into it. The team argued for nearly two weeks \u2014 should we use FPGA or go straight to ASIC? The focus of the argument really came down to one thing: power consumption.<\/p>

Everyone knows FPGA is flexible, but the power consumption genuinely keeps you up at night. We used a 16nm FPGA, running only a simplified FEC and fronthaul interface, and the core power supply alone on that single board ate up nearly 28 watts \u2014 add DDR4 and SerDes consumption, and the whole board ran hot like a winter hand warmer. Compare that against ASIC \u2014 running the same logic, a custom chip might not even draw 10 watts, doubling efficiency outright. But the pitfall with ASIC is you have to maintain an RTL team, cover front-end and back-end fully, and without a year or a year and a half, you won’t even see tape-out. And if volume isn’t large enough, mask costs alone can blow through the project budget.<\/p>

So in the end, we didn’t choose “which is better” \u2014 we chose “which can survive at this stage.” FPGA has higher power consumption, but at least you can get it on a board and debugging immediately, with software work proceeding in parallel. And we found a multilayer PCB manufacturer willing to grind through it with us, who helped us handle a 20-layer mixed-lamination board, routing those high-speed signal lines under the FPGA solidly and reliably. Honestly, in a project like this, the multilayer board supplier’s capability nearly determines success or failure. An average multilayer PCB supplier doing 14 layers is already decent, but fanning out hundreds of FPGA I\/Os while also controlling impedance and crosstalk \u2014 without real capability, they simply cannot deliver.<\/p>

I once chatted with a board shop’s engineer, and he said for boards like ours, the stack-up design is like building blocks \u2014 if the coupling between power layer and ground layer isn’t calculated precisely, the FPGA’s dynamic power fluctuation will directly pull the voltage off, and then timing closure becomes a nightmare. Sure enough, we later had a prototype revision that dropped packets while running, purely because power integrity wasn’t handled well \u2014 we ended up re-adjusting the stack-up, mixing several types of high-dielectric-constant board materials together, which finally suppressed the noise.<\/p>

Looking back now, if I had to choose again, I’d probably still go with FPGA validation first, but pull in the ASIC team early for pre-research. Because once the system is finalized, power and cost force you toward ASIC. Especially when your Central Unit PCB needs to fit into that compact outdoor cabinet form factor, with whole-unit power dissipation required under 50 watts, FPGA simply cannot hold up. At that point, the experience accumulated with that multilayer PCB manufacturer who could do 20-layer-plus high-precision boards becomes the most valuable asset when jointly debugging with the ASIC backend \u2014 after all, ASIC packages have more pins, and the demands on board-level design only get worse.<\/p>

So power consumption isn’t the sole criterion when selecting components, but it’s the thread that pulls at every decision. The chip you choose determines what kind of board shop you look for, and the board shop’s capability in turn limits what complexity of chip you can use. If this chain isn’t straightened out, you’ll be the one suffering in the end.<\/p>

A project I’ve recently been involved with landed right in the pitfalls of Central Unit PCB, and it gave me a completely different perspective on chip selection. I used to always think baseband processing in communications should naturally go the ASIC route \u2014 low power, cost can be brought down, and many chips internally hardened LDPC codec, DFT\/IDFT engines, sounding like they were custom-built for exactly this \u2014 not using them felt like a waste of all those specs. But once you actually get your hands dirty drawing the board and reach the multilayer board prototyping stage, you realize the real trouble has only just begun.<\/p>\t\t\t\t\t\t\t\t<\/div>\n\t\t\t\t

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The problem with ASIC chips is that they lock everything down. The reference design you get is usually based on a specific stack-up and specific material \u2014 switch to a different multilayer PCB supplier and things can go sideways. At the time we wanted to use a domestic ASIC for the O-DU central unit \u2014 the chip itself integrated eCPRI termination and modem functions, with densely packed pin layout, and a 12-layer board was already barely enough. The first prototype came back, and the SerDes eye diagram wouldn’t open at all, with ground bounce noise noticeably higher than simulation. After repeated troubleshooting with the multilayer PCB manufacturer’s engineers, we discovered the core board’s dielectric loss differed from the material in my reference design, and precisely because the ASIC’s high-speed interface link budget was so tightly constrained with no margin, we were forced to push the board from 12 layers to 14, re-adjusting the stack-up and return path before it barely passed \u2014 cost jumped substantially.<\/p>

This whole ordeal made me reconsider FPGA’s place in baseband processing. Many people think FPGA has high power consumption and high unit price, unsuitable for mass production, but it has one advantage \u2014 you can adjust interface logic and signal-processing chain at any time. We later put an FPGA next to an ASIC on another Central Unit PCB as a co-processor \u2014 the ASIC only runs hardened FEC and part of the DFT, while eCPRI termination and any algorithms needing flexible upgrades are all handed to the FPGA. This way, even if the fronthaul splitting method changes, I only need to modify logic \u2014 no re-tape-out needed, and no worry about a single chip holding the entire hardware architecture hostage. And the FPGA’s high-speed transceivers can be configured to adapt to different board materials and trace lengths, giving us room to work with different multilayer PCB suppliers without having to start worrying from the chip side every single time.<\/p>

Of course, this doesn’t mean ASIC is worthless. In some extremely power-sensitive scenarios where the standard has already frozen \u2014 like mass deployment of indoor small cells \u2014 ASIC combined with compact board-level design still has its value. But from a hardware engineer’s perspective, I lean toward designing the Central Unit PCB as a composable form: one core board carrying FPGA and necessary peripherals, with ASIC made as a daughter card connecting through a high-speed connector. This way, if communication standards ever shift again someday, or chip supply runs into trouble, I can at least keep the overall board-level architecture unchanged and just swap the daughter card. This approach actually raises the bar for multilayer board design even higher, because you need to control impedance discontinuities and connector stub effects within acceptable range \u2014 impossible without cooperation from an experienced multilayer PCB manufacturer.<\/p>

At the end of the day, chip selection can’t just be about paper specs \u2014 you have to weave the entire board-level engineering and supply-chain risk into your thinking. ASIC’s specialized performance is genuinely tempting, but once implemented physically on a Central Unit PCB, that “insufficient flexibility” shortfall often gives you a bigger headache than the power-consumption advantage written in the datasheet ever suggested.<\/p>

Many devices we use today, whether phones or base stations, have a Central Unit PCB inside that’s actually far more critical than most people imagine. I’ve taken apart plenty of boards and dealt with quite a few multilayer PCB manufacturers \u2014 honestly, very few shops can build this thing well. Many people think all you need is to solder a CPU or GPU onto it \u2014 but baseband processing’s requirements for the PCB are on a completely different dimension. A slightly imperfect high-frequency signal trace, and the whole link performance collapses \u2014 swap in a more expensive chip all you want, it’s still wasted.<\/p>

There was a period when I was particularly obsessed with moving baseband functions onto general-purpose computing, thinking stacking GPU compute could solve everything, only to later discover it wasn’t like that at all. At the hardware level, you need to simultaneously run high-speed digital signals and RF-related analog traces on the same board \u2014 stack-up structure, dielectric material, even copper foil roughness all affect the signal eye diagram. Among the multilayer PCB suppliers I’ve worked with, many got stuck controlling loss above 28GHz, and eventually we had to go back and revise the design, shrinking critical traces to the shortest possible, redoing the layering strategy entirely. This process made me realize the hardware backplane is actually the most “stubborn” part of the entire system \u2014 it can’t be rapidly iterated the way software can.<\/p>

There’s a tendency in the industry now to over-emphasize CPU or GPU compute power, as if with high enough FLOPS, baseband can be perfectly implemented in software. But the real situation is: run a 5G physical layer, and certain parallel decoding tasks can genuinely fly on GPU, but the moment you touch real-time scheduling and timing-sensitive eCPRI interfaces, a pure software solution runs into inexplicable latency jitter \u2014 jitter that is extremely painful to debug, because the problem often lies in the underlying hardware and driver interaction, not in upper-level code. So don’t just look at a chip vendor’s marketing \u2014 get the Central Unit PCB’s stack-up and power integrity solid first, and only then talk about software-defined baseband.<\/p>

Working in hardware for these years, I’ve increasingly come to feel that something is severely underestimated \u2014 the board that strings all the chips together. Especially now, as everyone chases GPU compute power and AI training, all eyes are fixed on core clock speed and memory bandwidth, and almost nobody bothers to look down at what their own Central Unit PCB actually looks like. This thing plays a role in AI servers and in 5G’s CU units far dirtier and more exhausting than you’d imagine.<\/p>

I helped a team doing inference acceleration look at their board last year \u2014 they’d bought the same high-end GPU, but power consumption was nearly 20% higher than a competitor’s, with the board hot enough to fry an egg. At first we thought the thermal module wasn’t seated properly, but peeling back layer by layer, the problem was in the PCB. They’d used a very cheap multilayer board supplier, whose stack-up structure never considered current density distribution under high-power scenarios \u2014 the result being insufficient inner-layer copper foil thickness, high power-plane impedance, and the GPU simply couldn’t draw clean power under dynamic load. At that point, no amount of driver tuning or AI model optimization helps \u2014 the physical layer is dragging everything down.<\/p>\t\t\t\t\t\t\t\t<\/div>\n\t\t\t\t

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So I’m now extremely sensitive about multilayer PCB manufacturer selection. Not by how pretty their website is, and not by how many certifications they list \u2014 but by whether they’ve actually built boards for sustained high-load, high-thermal-density scenarios. Some shops can only handle consumer-grade products \u2014 they’ll mark copper thickness as 1oz, but the actual product can vary by 20% edge to edge \u2014 that kind of board might be fine short-term for AI inference, but after a few months, vias crack and impedance drifts, with problems piling up one after another. A reliable multilayer PCB supplier needs to bring real measured data on high-power GPU platforms \u2014 for example, dielectric constant change rate at 85\u00b0C ambient, copper foil adhesion, and interlayer registration precision \u2014 these are what genuinely affect long-term stability.<\/p>

On power consumption, many people have a misconception, thinking it’s purely the GPU’s own business. Actually, a poorly designed Central Unit PCB can waste 3% to 5% of whole-board power just on the power distribution network. Doesn’t sound like much, right? But if you’re running a fully-loaded 8-card GPU AI training node, with each card at 300 watts, that 5% is 120 watts of wasted heat \u2014 plus the extra cost of cooling for it. Not to mention the hidden power consumption from bit-error retransmission caused by poor signal integrity \u2014 that portion simply can’t be monitored through software.<\/p>

In projects I’m currently involved in, if it’s AI-related hardware selection, I’d rather spend time repeatedly grinding through stack-up schemes with the multilayer PCB manufacturer than fix cooling later. I’ll require them to run electromagnetic simulation, pulling out the transient current for GPU, NPU, and high-speed SerDes for simulation, checking where power ripple exceeds spec. Sometimes just for how a power plane is split, I can argue with the engineer for a whole morning. But there’s no way around it \u2014 this is real, tangible power-saving, stability-improving work, not the kind of “optimization” that just draws pie charts on a PowerPoint slide.<\/p>

And with AI hardware’s current development direction, power consumption will only keep climbing, integration density only getting denser. Expecting chip process alone to hard-carry the power wall isn’t realistic \u2014 the real sweet spot actually lies in these foundational material and manufacturing processes. The day you see a board that can support a thousand-watt-plus GPU cluster while keeping power-supply loss under 2%, behind it there’s certainly a team that understands high-speed material and multilayer lamination process down to their bones. So stop just staring at the compute-power number \u2014 take a closer look at who made your PCB, and how \u2014 that’s the real root determining how stable and how long your AI system can run.<\/p>

Over the past couple of years, I’ve taken on quite a few projects requiring central unit PCBs, and my deepest realization is: if the board-level foundation isn’t solid, stacking any number of advanced chips on top is like building on sand. Many peers, when chatting, always steer the conversation toward heterogeneity, as if you’re not really doing hardware unless you cram FPGA, DSP engine, and processor all into one chip. But after actually running it a few times, you realize the trouble a single-chip heterogeneous solution brings a small team far exceeds the integration advantage it claims.<\/p>

I went through a fairly typical case: the team, wanting to save on a separate FPGA and several peripheral engines, chose a chip that crammed the ARM core, programmable logic, and DSP accelerator all into one package. For the first few months it did feel like the board was cleaner, and the central unit PCB was a size smaller. But midway through and later, the nightmare began. A power-timing conflict between one of the chip’s internal engines and the programmable logic section \u2014 the original FAE investigated for half a month and concluded “fixed in the next revision.” We could only wait it out, because you can’t fly-wire or swap a crystal to adjust things on the board the way you could with a standalone FPGA. For delivery timelines, that was pure, tangible loss.<\/p>

I later slowly formed my own judgment logic \u2014 not necessarily correct, but at least it helps avoid some pitfalls. I’d rather design the central unit PCB more carefully, find a multilayer PCB manufacturer that can do thin-board fabrication, control impedance, and mixed-lamination above 12 layers, get signal integrity and power distribution sorted clearly, then use standalone FPGA paired with separately procured hardware engines. This way every part is decoupled \u2014 the FPGA only handles logic processing, the engine specializes in acceleration, and the processor runs the protocol stack, with data flow strung together through a high-speed bus on the PCB. When something goes wrong, the troubleshooting scope narrows immediately, and I can swap multilayer PCB suppliers at any time to optimize materials, or adjust FPGA code, without being locked into a single chip’s closed ecosystem.<\/p>

The heterogeneous concept itself isn’t wrong \u2014 big companies genuinely run platforms like Versal well in data centers. But for most teams doing industrial equipment or edge terminals, the pitfalls buried are deeper than you’d think. The development environment needs to simultaneously master hardware description language and embedded Linux, which raises hiring costs by a notch. Not to mention that some heterogeneous chips’ DSP engines have sparse third-party IP support \u2014 if you want to build a custom filtering algorithm, you have to gnaw through the vendor’s underlying library yourself, far less efficient than hanging on a mature standalone engine.<\/p>

So now, whenever a newcomer asks about my design thinking, I don’t jump into chip selection right away \u2014 I first ask: how’s your communication with your multilayer PCB supplier going? Can details like layer planning, via type, and copper thickness actually be realized? These practical things are the real skeleton of a board. Get the central unit PCB’s foundation solid first, then evaluate the FPGA-and-engine combination \u2014 that’s far more important than diving headfirst into heterogeneous marketing talk.<\/p>

A project I’m currently working on, at its core, is a fight with a board. Once the RF front end was finalized, the part the whole team got stuck on longest was actually the central unit’s circuit board design. Initially we all thought, it’s just a Central Unit PCB \u2014 route it a bit denser, stack up the layers, find a reliable multilayer board manufacturer to prototype, nothing special. In practice, once we got our hands on it, it turned out to be nothing like that at all.<\/p>

The most tormenting part of this board wasn’t how many layers to stack \u2014 it was what core component to put on it. In our early evaluation, we hesitated for a long time between SoC and FPGA. For a while we kept feeling SoC was the trend \u2014 cramming everything into one chip, CPU core, DSP, even some hardware accelerators all squeezed together, feeling like it would make the board simpler. But once actually running, power consumption climbed, thermal layout fell into chaos right along with it, extra copper had to be added between board layers, and the entire power plane had to be re-planned. That’s when you realize the technical support a multilayer board supplier can give you matters far more than the “minimum trace width and spacing” marked on their website. A good supplier will tell you directly what differential impedance those groups of high-speed signals will drift to under a specific stack-up structure, rather than just sending you an impedance-calculation screenshot.<\/p>

We later switched to FPGA, and the problem became simpler instead. For the programmable logic portion, you can lock timing-critical modules using hardware description language, letting the ARM core slowly run the rest. But FPGA’s problem is it makes you too greedy \u2014 always wanting to cram in more functions, and once logic-resource utilization climbs, dynamic power consumption can’t be reined in. At that point you start wondering whether you should switch to ASIC. Honestly, ASIC’s threshold isn’t as forbiddingly high as before, but the premise is confirming your algorithm won’t change drastically \u2014 otherwise, the cost of one tape-out is enough to buy dozens of high-end FPGAs to slowly experiment with instead. I’ve seen peers grind hard on ASIC, only to end up with a batch of scrapped chips because algorithm iteration couldn’t keep pace \u2014 no matter how beautifully that board was designed, it was useless.<\/p>

So for this central unit board, which main control chip you choose almost determines your communication style with the multilayer board manufacturer. Going the SoC route, your layer count might be a bit lower, but power and thermal planning has to be front-loaded, and manufacturing tolerance has to be tightened further. Going FPGA, the high-speed transceiver routing on the board will have you repeatedly haggling over length matching and impedance details with the manufacturer. With ASIC, you often instead have to reserve more test points and jumpers at the board-design stage, leaving room for future debugging, because once there’s a bug inside the ASIC, you can’t reburn it like an FPGA \u2014 you can only try to patch it on the board.<\/p>

My current feeling is: there’s no absolute best option. Talk to hardware peers around you, and everyone will tell you the pitfalls they’ve hit. Some feel finding the right multilayer board supplier matters more than agonizing over chip selection, because if the routing doesn’t work, even the best chip won’t run. Other friends feel today’s capable multilayer board manufacturers already have process capability covering most digital and RF mixed-signal designs, and the real bottleneck is whether your understanding of your product’s algorithm is actually suited to being hardened directly. This is genuinely a grueling process, but that’s also what makes hardware interesting \u2014 it forces you to find a balance you can sleep soundly with, among space, power, cost, and future uncertainty.<\/p>

Not long ago I helped a team review their DU hardware design \u2014 the FPGA on the board took up nearly a third of the area, with a thick, heavy heatsink dragging down the entire chassis layout. I measured the power consumption \u2014 that accelerator card alone was pulling close to 60 watts, and that was before running the RF channels at full load. They originally wanted to use FPGA’s flexibility to adapt to different carriers’ frequency bands, but the result was that just getting the Central Unit PCB under that large-package FPGA sorted out took nearly four months. That board packed in over twenty layers, with dense high-speed SerDes routing \u2014 the slightest impedance deviation and the eye diagram closed up beyond recognition.<\/p>

Many people focus only on FPGA’s logic-resource capacity, forgetting the entire engineering cost behind it. You need to find a reliable multilayer PCB manufacturer capable of stably doing 2nd or even 3rd-order HDI, while also guaranteeing interlayer registration precision \u2014 there are only a handful of domestic shops that can take on this kind of order, and lead time routinely stretches past eight weeks. We switched through two multilayer PCB suppliers \u2014 the first batch of trial-production boards had a pile of shorts and opens, not even mentioning the micro-shorts hidden in inner layers. During debugging, boards burned out, FPGAs got scrapped right along with them, and all that cost went up in smoke.<\/p>

I eventually flipped the whole thinking around and forced the team back to the most fundamental question: how many units of this DU are you actually planning to sell? If it’s a small batch of a few hundred units, FPGA is still tolerable \u2014 power and cost get absorbed into the R&D budget, barely justifiable. But once you need to scale up, this FPGA-dominant scheme becomes a cash cow for the supplier. Go check \u2014 under equivalent logic capacity, FPGA’s unit price is how many times ASIC’s, and supply lead time entirely depends on someone else’s schedule. The moment geopolitical risk kicks in, lead time can jump straight from 12 weeks to 26 weeks \u2014 your Central Unit PCB materials are ready, the SMT line is set up, and all you can do is wait. That feeling is unbearable.<\/p>

I’ve increasingly come to feel that, at this stage, if you’re building a DU and the standard is already clearly a version after 3GPP R15, what you need isn’t the flexibility of anytime-reprogrammable logic \u2014 it’s stable, low-power baseband processing capability. Hardening the high-volume baseband and keeping it inside ASIC, while using lighter FPGA or simply an SoC with a built-in accelerator core to handle the fronthaul interface and reconfigurable modules, actually makes the entire hardware architecture cleaner. At that point, the Central Unit PCB’s layer count can come down too, from over twenty layers down to around sixteen, yield goes up, dependence on the multilayer PCB manufacturer isn’t as heavy, and the supply chain naturally becomes more resilient.<\/p>

I’ve seen too many projects get seduced by FPGA’s “universal” appeal from the start, thinking anything can be changed, anything can be adjusted, only to get stuck on the physical-implementation bottleneck in the end. The board can’t be built, cooling can’t be handled, and the moment power ripple gets even slightly large, the FPGA throws a tantrum, dragging out the entire DU integration schedule again and again. Rather than that, better to honestly harden the baseband and invest the saved engineering resources into software and system optimization. After all, what’s more expensive than one FPGA is opportunity cost.<\/p>

Working in hardware for these years, I’ve increasingly come to feel that a Central Unit PCB’s design, many times, determines the entire DU’s life or death. This isn’t scaremongering \u2014 go look at RAN equipment that runs stably in real networks, take it apart, and the core board’s routing and stack-up are almost always extremely carefully done. We had a project where, to rush the schedule, we casually found a multilayer board supplier for prototyping, and signal integrity turned out to be a complete mess \u2014 during FPGA and RF front-end joint debugging, the eye diagram was pathetically small, nearly driving the whole team crazy. We later switched to a multilayer PCB manufacturer with a good reputation in the communication board space, and they directly pointed out that our twelve-layer board’s stack-up design had a problem \u2014 the ground plane partitioning was unreasonable, causing excessive return loss on the high-speed serial link. This experience made it clear to me: what you’re choosing isn’t just a board \u2014 you’re choosing a multilayer PCB supplier who can pull you out of the mess when you’re losing your mind. Shops that just take orders and copy stack-up files, versus a partner who genuinely understands RF and digital mixed-signal design, are two completely different worlds.<\/p>

Many people now think using FPGA for acceleration in the DU is a flexible path \u2014 you can adjust logic anytime, adapting to different frequency bands. My own experience is that this flexibility is genuinely attractive at the early prototype stage, but once you move toward mass production and scale deployment, trouble comes. Timing closure has to be rerun over and over, power consumption can’t be brought down, and it’s hard to guarantee individual chip-to-chip variation across different FPGA batches won’t cause trouble. We ran a comparison \u2014 moving part of the beamforming processing from FPGA to a dedicated ASIC \u2014 though we lost programmability, whole-board power dropped by nearly 20%, without needing to fuss so much over the thermal structure. More critically, the DU’s operations team doesn’t actually need the underlying hardware to be that flexible \u2014 all they care about is that this board plugs in and stays fault-free for five years, without a hardened logic block suddenly failing and setting off a midnight alarm. FPGA’s iteration convenience, in real RAN deployment, can instead turn into a kind of technical debt.<\/p>

So now, when I look at any DU scheme, I first ask: how many years is this hardware platform actually intended to serve? If the lifecycle is only a year or two, using FPGA to stack features is fine; but if it has to follow the operator’s network-build pace, with a Central Unit PCB expected to hold up in an equipment room for seven or eight years, then from the PCB you get from the multilayer PCB manufacturer, to the FPGA model on the board, to the entire DU architecture \u2014 all of it must be chosen the most conservative, most reliable way. Don’t chase heterogeneous computing combinations that haven’t been validated at scale yet, and don’t believe any “software defines everything” universal narrative. RAN’s foundation is the physical world \u2014 signals don’t become obedient just because your software architecture is advanced; they only respect hard metrics like impedance matching, interlayer crosstalk, and power ripple. What we need to do is polish these hard metrics bit by bit, then let the board run quietly, without drawing attention to itself. That kind of solid groundedness is probably closer to the essence of communications than any fancy architecture diagram.<\/p>

In several projects I’ve been involved with over the years, Central Unit PCB selection, when the discussion finally settles, is often decided not by technical parameters but by what the multilayer PCB manufacturer in your hands can actually commit to. No matter how beautiful the stack-up structure looks drawn on paper, if the supplier says they can’t hit the impedance tolerance, or the minimum trace width and spacing simply can’t run, that whole pile of FPGA and ASIC choices becomes armchair theorizing. So now, when we build hardware, we always pull the multilayer PCB supplier in first for a sit-down \u2014 the board material, back-drilling precision, and copper thickness uniformity they can stably provide are what genuinely frame the boundaries of your solution.<\/p>

On power consumption, many people habitually stare at the TDP number in a chip datasheet, but what actually gives me a headache is how a high-current plane is distributed on the Central Unit PCB, and how to avoid thermally coupled regions. You might choose an SoC with even lower power consumption, but if the power network has severe voltage drop on the board, with local heating baking an adjacent high-speed signal’s eye diagram shut, that upfront low-power selection was wasted. Our previous design revision fell into exactly this trap; we later switched to a multilayer PCB manufacturer supporting 2oz thick copper plus embedded copper block, and with the same hardware setup, supply noise and hotspots in the thermal image both quieted down considerably.<\/p>

Hardware selection, I increasingly feel, is a convolution of experience rather than a linear comparison. For instance, some people like going all-FPGA on a Central Unit PCB for flexibility; others insist on ASIC to save power. But in reality, if the multilayer PCB supplier you found is strong in high-density interconnect, then FPGA’s fanout and wide bus become easier to handle; if their strength is large-size heavy copper boards, then a more rugged, high-current ASIC scheme might be more reliable. You can’t discuss chip pros and cons in isolation from the supply chain \u2014 that’s far too idealistic.<\/p>

One more thing \u2014 power and thermal design on a Central Unit PCB absolutely cannot wait until after layout is finished to patch in. My current habit is to lay the estimated power-density map and candidate multilayer PCB supplier’s thermal-solution capability side by side right at the selection stage \u2014 for instance, can they do metal-core substrate, can they do thermal-via array filling. Sometimes a component with a hotter package but lower internal resistance, paired with a multilayer PCB manufacturer who understands thermal management, ends up delivering better overall performance than a nominally “low power” chip that’s cold on paper. Hardware was always a string of compromises to begin with, and the Central Unit PCB is the final physical arbiter \u2014 it can turn all your clever selections into reality, or it can bring them all crashing down.<\/p>\t\t\t\t\t\t\t\t<\/div>\n\t\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t<\/div>","protected":false},"excerpt":{"rendered":"

Months of eCPRI packet-loss debugging on an O-DU project kept leading back to the same place \u2014 not the FPGA, but the multilayer PCB manufacturer’s stack-up and copper foil roughness. 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