{"id":12088,"date":"2026-11-02T15:01:00","date_gmt":"2026-11-02T07:01:00","guid":{"rendered":"https:\/\/www.sprintpcbgroup.com\/?p=12088"},"modified":"2026-11-02T11:37:29","modified_gmt":"2026-11-02T03:37:29","slug":"cxl-interconnect-pcb-hdi-heavy-copper-supplier-selection","status":"publish","type":"post","link":"https:\/\/www.sprintpcbgroup.com\/fr\/blogs\/cxl-interconnect-pcb-hdi-heavy-copper-supplier-selection\/","title":{"rendered":"CXL Interconnect PCB Supplier Guide: Balancing HDI Routing, Heavy Copper Power and 32GHz Signal Integrity"},"content":{"rendered":"\t\t
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A CXL Interconnect PCB is a multilayer board that must carry high-speed PAM4 differential signals and heavy memory-expansion current at the same time. Manufacturers that can deliver both HDI fine-line routing and heavy copper power layers in one factory are rare. Board-level decisions such as laminate loss, copper foil roughness, via stubs, impedance tolerance, copper thickness and thermal paths often matter more to real-world CXL latency and stability than protocol-level tuning.<\/p>

Why CXL Interconnect PCB Supplier Selection Comes Before Channel Simulation<\/h2>

When building CXL interconnect boards, many of my peers dive straight into PAM4 channel simulation and tune eye diagrams until they are sick of them. After several years of working on this, my biggest takeaway is the opposite: you first need to work out what kind of board manufacturer you are looking for. CXL runs on PCIe 6.0, so in essence it is a multilayer-board monster, and it needs to carry current as well as run fast. I once worked with a multilayer PCB supplier whose high-speed capability was acceptable, but whose heavy-current copper thickness for the memory expansion section simply fell apart. The result was either a huge voltage drop or a board as hot as an electric stove. In the end I had to split the job between two vendors, one doing HDI for fine-pitch routing and the other doing thick copper dedicated to the power layers. Costs nearly doubled and the lead time was lost to coordination. That is when I understood how rare it is to find a manufacturer that can handle both HDI processes and heavy copper properly.<\/p>

A CXL Interconnect PCB carries an x8 link at 3.2T running at a 32GHz Nyquist frequency, and it also has to supply tens of amps to a stack of DDR5 memory chips, so thin copper foil cannot get away with it. Many engineers focus on the few nanoseconds of latency in the protocol stack and overlook the hard board-level problems: without a reliable high-layer-count board manufacturer, you cannot even maintain basic power integrity. With PCIe you can still muddle through with ordinary high-layer-count boards, but once CXL adds memory pooling, board-level heat and copper-thickness current capacity push you straight to the door of a heavy copper PCB supplier. I have screened quite a few multilayer PCB manufacturers over the years. Those that can do thick copper and laser blind vias well inside a single factory can be counted on one hand. Among HDI PCB suppliers in Asia that specialize in high-mix processes, I did dig up two that could hold yield above ninety percent.<\/p>

At the end of the day, however strong the chip protocol is, if it does not land properly on the board it just spins its wheels. The thermal structure of the memory expansion section relies on thick copper to spread heat out, while high-speed signals force you to use low-loss substrates with fine lines. Without a manufacturer that has built both high speed PCB and heavy copper PCB, no matter how well you have mastered the protocol, the prototype will run happily and then fail as soon as you go to volume production.<\/p>

Latency, Dielectric Constant Tolerance and Why the PCB Channel Matters<\/h2>

With CXL boards, the headaches are not at the protocol layer but in the invisible, intangible physical layer. Every time we measured memory expansion latency we stared at a gap of a few dozen nanoseconds, and in the end we found that half of the blame belonged to the PCB channel. The ideal CXL memory access latency is about 75 nanoseconds, but that is the ASIC playing by itself. Once you count trace length, vias and connectors, plus the few nanoseconds introduced by a retimer, it is not surprising that a real system ends up a bit above 800 nanoseconds. So when I choose a multilayer PCB manufacturer, I basically do not look at how many layers they advertise. I ask directly which grade of core they can use in the stackup and whether they can hold dielectric constant tolerance within plus or minus 0.05. PAM4 is so sensitive to impedance variation that even slightly uneven local resin content in a glass bundle can collapse one corner of the eye.<\/p>

Many people believe a CXL Interconnect PCB is no different from an ordinary server board, and that is the biggest misunderstanding. Our earliest validation board used conventional high-Tg FR-4, and the channel insertion loss at 16GHz exceeded the limit by 3 dB, so link training failed repeatedly. We then switched to a low-loss material and had a manufacturer with more than ten years in HDI PCB re-prototype the board. We optimized the antipads of differential vias into an elliptical shape and controlled the backdrill depth so the remaining stub was under 6 mil, and only then did return loss fall below -20 dB. None of these details can be solved by the automatic routing of EDA tools. It also made me adopt a habit: whenever high-speed differential pairs cross layers, I press the board manufacturer to provide batch test data for the actual dielectric constant and loss tangent of each layer, and if they will not supply the data, I change supplier.<\/p>

Power Density, Heavy Copper and Thermal Design for CXL Type-3 Boards<\/h2>

Another maddening thing about CXL is power density, especially on Type-3 memory expansion cards, where the hot-spot temperature of the on-board FPGA or dedicated controller can spike instantly. We used to think ordinary 2oz copper would be enough, but the thermal simulation showed a junction temperature approaching 100 degrees, and we had to take the heavy copper PCB route. I stepped on a few mines while looking for a heavy copper PCB supplier. In some factories, so-called heavy copper simply means thickening the outer-layer copper pour while the inner layers remain a conventional half ounce, which cannot carry away heat buried in the middle layers. Later we standardized on a thick copper PCB manufacturer that could do 4oz copper on inner layers. We placed a full-surface thick copper plane on layers L3 and L5 as a thermal conduction plane, used copper-plugged thermal vias, and added thermally conductive filler on the bottom side, which brought the temperature rise near the controller down by 15 degrees. The coupling between power integrity and heat on a CXL board is often underestimated.<\/p>

Memory Trace Length Matching and Latency Jitter<\/h2>

The memory side is even more subtle. On one design, to meet a schedule, we left the trace lengths from the CXL controller to the memory chips inconsistent, with the longest and shortest differing by nearly 800 mil. As a result, memory access latency jitter was 10 nanoseconds greater than expected. Do not underestimate such a small fluctuation. For a memory pool across NUMA nodes, it can mean that remote access latency jumps from 850 nanoseconds to nearly 1 microsecond, and performance degrades directly. That board had to be scrapped and redone. We found an HDI PCB supplier that could precisely control trace length tolerance to plus or minus 1 mil, and used an any-layer interconnect HDI structure to compress the length difference of the whole DQ group to within 2 picoseconds. This is how high-speed digital work goes: the schematic only draws logical connections, but in reality every millimeter of trace is real time, and the CXL memory latency budget gives you no room for error. So whether I am choosing a multilayer PCB supplier or doing board-level simulation, I now split the whole link into three segments, channel, retimer and protocol processing, and fight hard over latency in each. Those few nanoseconds are real performance.<\/p>

Low-Loss Materials, Backplane Failures and Why Batch Consistency Matters<\/h2>

Last year I helped a memory-pooling team build a CXL backplane and nearly developed a psychological shadow from board material loss. The board originally used standard FR-4, and at the 32GHz Nyquist frequency of the signal the waveform simply could not hold up; the eye was closed tighter than an old-fashioned venetian blind. For a CXL Interconnect PCB, the physical layer directly inherits 64GT\/s PAM4 signaling, and the link loss budget is held very tight. Many people assume that driver-side equalization can brute-force through it, but in volume production the ten or twenty dB left for the PCB can be mostly swallowed by a single via transition or a section of microstrip.<\/p>

At the time we could not figure out why differential pairs that barely worked at prototype stage saw their bit error rate soar once the boards went to formal production. Later we sent the board to a third party for cross-sectioning and found that the multilayer PCB manufacturer had used prepreg from different batches during lamination. The dielectric constant deviation had shifted impedance beyond the design value. That incident taught me a lesson: not every multilayer board supplier deserves to take a high-speed digital board, especially on the CXL path, where once the supply chain for materials with Df below 0.002 has a problem, the loss budget becomes a joke.<\/p>

So later, whenever I release drawings, I directly require the high speed PCB manufacturer to provide measured S-parameter curves from 1GHz to 40GHz, and they must come from data sampled on production boards, not simulations. When reviewing, I especially watch whether insertion loss suddenly falls off a cliff between 26GHz and 32GHz. That usually means the stub was not backdrilled clean, or a reference layer was split and the return path was damaged. In theory the phrase excessive return loss covers these things, but troubleshooting on site can keep you up all night.<\/p>\t\t\t\t\t\t\t\t<\/div>\n\t\t\t\t

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Copper Thickness Versus Loss in Mixed Heavy Copper and High-Speed Designs<\/h2>

Another easily overlooked point is the tug of war between copper thickness and loss. Memory expansion often needs high-current power, which cannot avoid heavy copper PCB, even designs with 3oz copper or more. For a while we fantasized about asking a thick copper PCB manufacturer to make the power distribution layers thick directly while keeping signal layers thin copper, only to find that at high frequency, the thicker the copper, the more obvious the conductor loss caused by skin effect, especially once copper foil roughness gets out of control and the loss curve drifts upward. Later we talked with a heavy copper PCB supplier and arrived at a balance: sandwich the high-current copper between two independent ground reference planes in the inner layers, use only HDI blind and buried via fan-out on the top and bottom layers, and keep signals entirely on thin-copper, low-loss layers.<\/p>

HDI Supplier Capability Differences in High-Frequency CXL Boards<\/h2>

Speaking of HDI, I believe the capability differences among HDI PCB suppliers get magnified without limit on high-frequency CXL boards. Some vendors use laser drilling and can make 0.1 mm holes, but their backdrill accuracy cannot keep up. Stub length then wanders, and signal eye height is eaten by twenty or thirty percent. I compared three or four HDI PCB manufacturers and found that those with long-term volume production experience on phone motherboards actually control microvia formation more reliably than pure high-speed board shops. In the HDI process, the plating uniformity of microvias and the alignment of the via-bottom pad directly affect via impedance continuity, and in the short-channel design of CXL that is more fatal than material loss.<\/p>

Looking back now, loss has never been an isolated signal integrity problem. It extends from the consistency of incoming materials, through the multilayer PCB manufacturer’s stackup control and copper foil roughness management, to the shape of solder joints after assembly. I once saw a thick copper PCB where the copper in the heat-dissipation area was so thick that heat capacity was uneven during soldering, leaving one corner of a BGA with cold-soldered balls, and the whole CXL channel broke during thermal cycling testing. You cannot blame anyone for this kind of problem; it only means the process boundary was never taken into account in the physical channel budget at the beginning of the design.<\/p>

Later I gradually formed a habit: before drawing the first schematic, I go to the multilayer PCB supplier and pull their engineering capability data to see what level of impedance tolerance, backdrill accuracy and resin-filling capability they can deliver stably in this regime. Instead of wrestling with loss values afterward, it is better to let the process margin of the PCB manufacturer cover you proactively. Choosing the right supplier is more useful than running another ten simulations.<\/p>

Copper Foil Roughness and Why Datasheet Loss Figures Do Not Match Finished Boards<\/h2>

I have spent the last two months tangled up in a CXL Interconnect PCB project and stepped on enough mines to fill a notebook. A common phenomenon in this trade is that whenever people talk about high-speed channels, their minds are nailed to the Df value of the material, as if switching to a low-loss laminate could cure everything. I contacted several HDI PCB manufacturers that claimed to handle high speed. They patted their chests at quotation time and said no problem, but when the boards came back and went onto a vector network analyzer, insertion loss at 32GHz could not be squeezed into the budget, and I watched the eye collapse into a blob. Where was the problem? Ultimately, the manufacturing side had not taken copper foil seriously.<\/p>

Many people overlook a very practical issue: the loss figure written in the datasheet for the laminate you get from a multilayer PCB supplier was measured before lamination, which is a different thing from the finished board. Once the board is actually built, a large share of the loss is eaten by copper foil surface roughness, and the higher the frequency the more obvious it is. I have tried more than one multilayer PCB manufacturer and asked whether they have established control over copper foil roughness. They either could not produce specific data or simply said that standard copper foil is like this and I could take it or leave it. In the end I had to accept the risk myself and tweak equalization parameters with my teeth gritted, which left me in a sorry state.<\/p>

Now, with a loss-sensitive design like CXL, I basically do not go to a factory that only does HDI PCB supply, even if its HDI process is mature. HDI factories are good at microvias and fine lines, but their understanding of signal integrity is often superficial, and their choice of copper foil type is conservative. By contrast, some high speed PCB manufacturers that specialize in high-speed backplanes will ask, without being reminded, whether you want HVLP copper foil and whether the glass cloth needs flattening. They know that at 32GHz the skin depth is tiny, and that the bumps on the copper foil surface are a real source of loss. This kind of experience follows a completely different logic from making ordinary circuit boards.<\/p>

Combining CXL Channels and Power Sections on One Board<\/h2>

Copper foil and materials intertwined are sometimes more of a headache than choosing the laminate alone. I once tried to integrate the CXL channel and the power section on one board and asked a heavy copper PCB supplier to do a hybrid lamination, and the test data on the finished board was dismal. The copper foil used on the thick copper layer was absurdly rough, which directly raised insertion loss of the whole link by a notch. Later I talked with an engineer at a heavy copper PCB manufacturer, who was very frank: the thick copper process focuses on current capacity and thermal management, and roughness has never been a priority metric. A thick copper PCB manufacturer is even more typical. Mention Rz or Rq and they look blank, because what they deal with every day are multilayer power boards or motor-drive boards, and high-speed signals are not their world. After that lesson, whenever a design has both high current and high-speed channels, I would rather split the board than rely on a do-everything supplier to resolve all the contradictions.<\/p>

In the end, material decisions cannot rest only on the curves supplied by the vendor. Loss is the product of copper foil, dielectric, glass weave and even the lamination process all tangled together. When selecting partners now, I value more whether they can explain their whole process clearly and whether they have real volume production data, rather than opening with the brand of laminate they use. Those multilayer PCB suppliers who drone on about using top-grade materials often steal key work in places you cannot see. A truly reliable factory will instead consider the manufacturability window for you and tell you where to compromise and where to fight to the death. The trust built through long-term running-in is worth more than a datasheet.<\/p>

HVLP Copper Foil, Peel Strength and Reliability<\/h2>

After so many years building high-speed digital boards, what gives me the most headaches is not signal integrity theory but turning theory into physical products that can be produced stably. A CXL Interconnect PCB design these days often demands HVLP copper foil with Rz pressed below 2 microns, which looks nice because insertion loss does save a few tenths of a dB. But anyone who has run production batches knows that looking only at the copper foil model is useless. I have seen too many multilayer PCB suppliers stick HVLP on a specification sheet as a label, and when the boards are in hand and peel strength is tested, it cannot even hold 0.8 N\/mm, and blisters appear right after thermal cycling. The key lies in the interface treatment between the copper foil and the base material, which cannot be solved merely by swapping in a low-roughness foil.<\/p>

So now I actually feel more at ease with multilayer PCB manufacturers that dare to control roughness at around 3 microns while still reaching full peel strength. Over-pursuing a mirror-grade surface sacrifices long-term reliability. Especially in high-power areas or areas that need to carry large current, we more often work with a heavy copper PCB manufacturer or a thick copper PCB manufacturer on a hybrid lamination design: low-roughness copper foil on signal layers and thick copper directly on power layers. This is far more pragmatic than simply changing every layer to HVLP2. Some heavy copper PCB suppliers provide thick copper boards whose foil is naturally rougher, but by improving the lamination process they can still keep the overall channel loss no worse than an all-HVLP board, because they reduce the number of vias and the backdrill depth.<\/p>

Backdrilling, Residual Stubs and Stackup Planning<\/h2>

On backdrilling, residual stubs have been hyped far too much by solution vendors. I admit that a 20 mil stub creates a resonance notch at 32GHz, but it is not the only channel killer. Rather than fighting to the death with an HDI PCB supplier over 5 mil backdrill accuracy, it is better to place signal layers in the middle-to-lower part of the stackup during the stackup design phase, so that stubs are naturally shorter than 8 mil and do not depend on backdrilling at all. This is a test of the layer-to-layer alignment capability of the HDI PCB manufacturer, but a good manufacturer can do it. The first thing we do after getting boards is not to put them on a VNA but to cut cross-sections and check the uniformity of copper thickness and the batch-to-batch fluctuation of roughness. Once roughness rebounds, the signal margin you saved earlier is wasted. At the end of the day, high-speed design depends more on choosing the right high speed PCB manufacturer than on staring at one or two indicators.<\/p>

CXL 3.0 Specifications Versus Manufacturing Reality<\/h2>

What I cannot stand most after so many years of high-speed boards is forcing theoretical parameters onto actual manufacturing, especially the indicators recently pushed by CXL 3.0. The specification documents read so lightly: stubs below 6 mil, impedance tolerance tightened to 5%, as if a factory could do it as easily as playing a game. But if you really sit down with several multilayer PCB manufacturers, their first reaction is almost always the same: this will cost extra, and nobody dares to guarantee yield.<\/p>

Take the stub first. The specification of course wants it as short as possible, ideally eliminated altogether. A blind and buried via approach is indeed clean by design, but on a CXL Interconnect PCB with more than twenty layers, the number of lamination cycles alone can make a multilayer PCB supplier cry over scheduling. On my last validation board, to save those lamination cycles, I gritted my teeth and used all through holes plus backdrilling. A fairly reliable high speed PCB manufacturer delivered the first batch, and backdrill depth consistency overturned the cart. Their CNC drilling machines can in theory reach two or three mil of accuracy, but in real volume production, the accumulation of errors from tool wear and board dimensional movement is nothing like the laboratory. One batch was backdrilled too deep and almost gnawed into the power copper of the adjacent layer, and the measured eye closed as if it had been drawn with closed eyes.<\/p>

Impedance is an old topic, but CXL’s 5% requirement on 85 ohm differential impedance simply corners many HDI PCB manufacturers that claim to make precision boards. I have seen factories that at sampling stage could control line width to within plus or minus 0.5 mil under a microscope, but once in volume production the impedance values measured at different positions on batch boards started to dance. Is their process poor? Not exactly; real money in costs sits behind it. To get uniformity across the whole board you need a better grade of base material and stricter process control, and every step burns cash. The quotation that finally comes out will make you wonder whether you should change that portion of the circuit to a separate power supply on a thick copper board from a heavy copper PCB supplier, where at least the power section is sturdier.<\/p>

Where to Relax Tolerances and Where to Insist on Premium Fabrication<\/h2>

Many times designers fall into perfectionism, as if failing to push every parameter to its limit would betray the specification. In my experience, if the budget is not unlimited, you have to learn to use boards from the best HDI PCB supplier on the critical signal chain and apply reasonable derating elsewhere. For example, in some non-core routing areas, negotiate with the multilayer board manufacturer to relax impedance tolerance to about 8%, and compensate by adjusting routing density; overall performance then becomes more controllable. I once encountered a case where an entire board was ordered at plus or minus 5% from one multilayer PCB manufacturer, and to guarantee that tolerance they changed the process in other places we did not notice, leaving the board with excess warpage that failed the shock test.<\/p>

Splitting the Design Into a Daughter Card and a Heavy Copper Base Board<\/h2>

Speaking of thick copper, many people think it has nothing to do with CXL high-speed signals, but I increasingly lean toward splitting the whole board into a daughter card plus base board structure. The core compute card uses fine lines, while a factory skilled as a heavy copper PCB manufacturer makes the power distribution base board; thick copper conducts heat and current reliably there, and impedance challenges do not spread to the precious signals above. Is it expensive? It is far cheaper than the rework and scrap costs of cramming everything into one 32-layer board. Some thick copper board makers can now also do precision patterns, but if you ask them to deliver sub-6 mil stubs and the copper thickness uniformity required of a thick copper PCB manufacturer at the same time, they will say yes, but the actual delivery time can drag until your product is half dead.<\/p>

So my thinking is simple: do not order physical limits off a menu. Work out what you really need to protect and compromise on the rest. For a reliable multilayer PCB supplier, the most frightening thing is not a customer with high requirements but a customer who demands everything be high and pushes laboratory extremes into volume production. For a new interface like CXL, in the first year or two of board-level implementation, working out a practical process boundary together with the factory is far more meaningful than copying the specification verbatim.<\/p>

Glass Weave, Lamination Uniformity and Copper Thickness Capability<\/h2>

In my years of working on CXL Interconnect PCBs<\/a>, I have noticed an interesting phenomenon: too many people spend their energy on glass cloth selection, as if signal eyes will certainly be shut tight unless spread glass cloth is used. In reality it is not that absolute. I have worked with several high speed PCB manufacturers and stepped on pits too, and so far it looks like getting the multilayer PCB supplier’s lamination uniformity and copper thickness capability right is often far more useful than fighting over glass cloth type.<\/p>

For example, one project needed a CXL high-speed link with more than ten amps of continuous current, so the board had to use heavy copper. We chose a factory specializing as a heavy copper PCB manufacturer, with inner-layer copper pulled directly to 4oz, and through step-by-step etching and pulse plating they kept line width tolerance within plus or minus 8%. At that point you find that the influence of copper foil thickness and dielectric layer uniformity on impedance far outweighs the periodic dielectric constant fluctuation caused by glass weave. In that case we did not use particularly expensive spread glass cloth; we used ordinary 1067 glass cloth, and in layout let differential pairs keep a small angle of 7 to 12 degrees to the warp and weft. The measured intra-pair skew was under 3 ps, completely sufficient. You may say that was luck, but if the lamination level of the multilayer PCB manufacturer itself is poor and the prepreg flow leaves uneven thickness, then even with the best glass cloth the impedance will still wander.<\/p>

Later, some peers in the HDI field described similar situations. The HDI PCB supplier they worked with immediately recommended expensive mechanically spread glass cloth, claiming it could press jitter to the extreme. But that HDI PCB manufacturer’s laser drilling and via filling for small-pitch BGAs was not yet mature, so the probability of micro short circuits in finished boards rose noticeably, and the final scrap rate came out four or five points worse than expected. That says a lot: on a high-speed channel like CXL, you cannot look at glass fiber alone as a single variable; the supplier’s control over the whole process chain is the bottom line. In another case, we needed the capability of a thick copper PCB manufacturer for power layers while also handling high-speed signals, and ended up choosing a multilayer PCB manufacturer that used NE-glass with an improved semi-additive process, which could handle fine lines and provide enough copper thickness. We did not bother with those fancy special glass cloths, and it still passed 32Gbps signal integrity verification smoothly.<\/p>

What I have gradually figured out is that the bottleneck of a CXL interconnect board is often not in the hyped-up material details but in whether the supplier you choose can laminate ordinary glass cloth, copper foil and prepreg into a board steadily. If the board stock you receive has uneven copper thickness and dielectric thickness undulating like hills, the glass weave effect is the smallest of your troubles. So when anyone asks me now where to start on a CXL project, I usually say: first find a heavy copper PCB supplier or a high-layer-count board factory that can handle copper thickness and stackup tolerance, then fine-tune routing angles according to the actual stackup, and glass cloth of type 1067 or ordinary low-skew grades is about enough. There is truly no need to be led astray by the blanket of technical articles and complicate a simple problem.<\/p>

Connector Breakout Regions and Impedance Continuity on CXL Backplanes<\/h2>

After years of building high-speed backplanes, I increasingly feel that one thing is widely misunderstood. When people discuss CXL interconnect, their attention is almost entirely on connectors, as if sorting out the impedance continuity of interfaces such as SFF-TA-1002 would make the link budget stable. In reality, the few millimeters running down from the connector pad are the true mirror that shows up the whole channel.<\/p>

I have dealt with several multilayer PCB manufacturers, and after the sample boards came back and I measured them, the impedance curve of the differential line near the connector jittered like an electrocardiogram. The problem was not the connector itself; it was that the PCB factory, in handling pad antipads, breakout angle and layer-to-layer registration, had accumulated deviations to an unacceptable extent. With PAM4 signals in particular, an eye closed by half is already being polite. Later we switched to an HDI PCB manufacturer<\/a> that specifically takes on hard problems, and things improved markedly. They used an improved semi-additive process to control line width accuracy, and the position deviation of laser blind vias and stacked vias could be held within 40 microns, which has a huge influence on the parasitics of the connector transition. So now when I choose an HDI PCB supplier, I do not look at how many layers it advertises; I ask directly: have you done full-link simulation data for a CXL Interconnect PCB, and how much of a guarantee can you give for discontinuities like connector pads?<\/p>\t\t\t\t\t\t\t\t<\/div>\n\t\t\t\t

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Heavy Copper Power Layers and Dielectric Thickness Compression<\/h2>

Another point easily neglected in high-speed design is the power layer and copper thickness. AI chassis backplane currents are frighteningly large, and many solutions need a heavy copper PCB supplier to provide inner-layer copper of 4 or even 6 ounces to carry high-voltage, large current. But the problem arrives immediately: the dielectric thickness between the thick copper layer and the adjacent signal layer is forced thinner, and crosstalk and impedance control deteriorate at once. I have seen with my own eyes a project where a thick copper PCB manufacturer pressed the copper foil too tightly, so that the distance from the microstrip to the reference plane changed from the designed 4 mil to 3.2 mil, and differential impedance dropped straight to 85 ohms, and no tuning on the connector side could rescue it. Later we simply placed the heavy copper layers separately in an area away from high-speed signals, found another heavy copper PCB manufacturer to re-prototype, and used embedded copper blocks plus thermal pillars to handle current carrying, while the signal layers returned to conventional copper thickness, which finally opened the eye.<\/p>

In other words, when choosing multilayer board suppliers for a CXL link, you cannot just look at whether it is a listed multilayer PCB supplier. You have to ask whether they have made boards mixing high-speed and heavy copper, and whether they know how to handle a connector transition region. Whether to choose M6 or M7 grade for high-speed material, and how much the dielectric constant drifts after reflow, are all details any one of which is more lethal than the connector specification itself. However excellent the SFF connector is, what ultimately decides the link is the process ceiling and engineering conscience of the PCB manufacturer.<\/p>

Retimers, Clock Routing and Why Channel Quality Comes First<\/h2>

The biggest feeling I have from CXL interconnect projects over the past two years is that people too easily treat the retimer as a wild card. If channel signal quality cannot hold, stack a retimer; if timing closure does not converge, add another. The board is crammed full, BOM cost soars, and then the thermal simulation runs and leaves you stunned. In fact, many problems are not about whether to add a retimer at all; they come from not sorting out the relationship between clock and channel when the CXL Interconnect PCB was first drawn.<\/p>

CXL is far more sensitive to clock jitter than ordinary PCIe. Its flit mode switching back and forth depends entirely on the cleanliness of the reference clock. If a multilayer PCB manufacturer<\/a> skimps on the stackup to save cost, running clock traces under split planes or sending the GND return around a big detour, link training will report errors again and again. If at that point you do not trace the root cause and tear the stackup down to redo it, but instead use a retimer to forcibly wash the signal, it is simply paying a high price for comfort. When I build high-speed boards, I would rather route clock traces through two extra layers to keep them against a complete ground plane the whole way, even if the high speed PCB manufacturer has to trim copper twice more, to keep reflection and crosstalk to a minimum.<\/p>

The idea of segmenting the channel is not wrong, but do not default to the assumption that you must cut. My habit is to talk first with an HDI PCB supplier, the people who do HDI, because their laser drilling and blind and buried via accuracy lets differential pairs be made very compact, and the channel loss itself can fall considerably. On one 112Gbps CXL pre-research board, I used a local HDI PCB manufacturer I knew well to prototype, adjusted copper foil roughness and dielectric thickness, and managed to hold the total insertion loss of the whole backplane link near 32 dB. The two retimers originally planned were cut directly, and the clock tree became as clean as a white shirt just out of the washing machine. The extra board space went to the power delivery network, with additional thick copper laid, made by a heavy copper PCB supplier specifically for those power areas, and under high current density the voltage drop was less than half the requirement. The satisfaction of controlling channel quality at the source is far greater than propping it up with retimers.<\/p>

Mixed Copper Weights, Supply Noise and Retimer Count<\/h2>

Today the processes of heavy copper PCB manufacturers and thick copper PCB manufacturers are much more mature than a few years ago. They can directly mix different copper thicknesses within the same stackup, with standard copper foil on signal layers and 4 or even 6 ounces on power layers. This is a real improvement in supply ripple suppression for CXL controllers and retimers. With clean power, the PLL inside the retimer is not jerked around by supply noise, and in turn there is no need to rely excessively on CDR to brute-force through, which is the proper design closed loop. However, I have seen many designs where signal integrity is already a mess while the power layers are stingy, and a pile of retimers is crammed in anyway, leaving the board big and hot and the whole project’s space and power budgets swallowed. Every time I see such a layout, I want to push the board back and tell them to grind the stackup table three more times with the multilayer PCB supplier first.<\/p>

Clock Path Planning and TDR Reports Before Retimer Discussions<\/h2>

Clock path planning ultimately has to be rooted in PCB physical implementation. If you find a reliable multilayer PCB manufacturer that can hold clock trace length matching within 5 mil and keep backdrill residue to 0.2 mm, the deterministic jitter in the channel is no threat. However good the retimer is, if the layout of its own 100MHz reference clock is not handled properly, the random jitter added to the signal becomes a new problem. Sometimes when a board cannot be brought up and engineers frantically tweak CTLE parameters and swap equalization algorithms, I glance at the impedance test report sent by the PCB factory and almost have a heart attack on the spot: differential impedance deviation has reached 15%, beyond saving by any god. So I now set a rule for the team: any signal-conditioning device on a high-speed channel may be discussed only after the PCB process is confirmed to meet requirements; if the TDR report from the multilayer PCB supplier fails, nobody mentioning a retimer gets my signature.<\/p>

This is ultimately a matter of the order of design philosophy, not that the devices are bad. Raising the ceiling of the channel itself is far more cost-effective and reliable than stuffing compensating devices into the channel. For a protocol like CXL that demands extreme latency and bandwidth, each extra retimer on the board adds nearly ten nanoseconds of delay, and accumulated together the memory access latency distribution widens as a whole, wasting all the software-level optimization.<\/p>

How CXL Raises the PCB Design Threshold<\/h2>

After so many years in high-speed digital circuits, one feeling grows clearer: CXL is sharply raising the threshold of PCB design. Memory interfaces used to be parallel buses like DDR, and once impedance was controlled and lengths were matched you were basically stable. Now CXL runs on the PCIe physical layer but carries memory access semantics that are extremely latency-sensitive, and the situation is completely different. Routing one extra inch on the board may directly eat a chunk of a budget of a few dozen nanoseconds, and for memory pooling, every nanosecond is being squeezed.<\/p>

In the projects I have touched recently, many teams have begun to hesitate to use ordinary multilayer solutions. It is not that an ordinary multilayer PCB manufacturer cannot do high speed, but that CXL’s signal integrity requirements have reached the point where even a slight discontinuity in a reference layer collapses the eye beyond viewing. At 32Gbps or higher, via stubs are no longer an issue where it would be best to optimize a bit; they are zero tolerance. That means your multilayer PCB supplier must precisely control backdrill depth, with the remaining stub no more than a few mil, which tests process stability severely.<\/p>

High Density Versus Heat in Controller and Memory Power Design<\/h2>

Interestingly, a rather twisted relationship has begun to appear between high density and heat dissipation. To shorten traces and control latency, one naturally thinks of an HDI PCB supplier solution, using microvias to quickly fan out the pile of high-speed lines under the BGA and make layer switching more flexible. But the CXL controller and memory chips consume considerable power, and power integrity has to be carried by brute force. At that point some designs introduce heavy copper: find a reliable heavy copper PCB manufacturer to do thick copper processing on inner layers, which carries large current and also serves as a heat path. But thick copper is a double-edged sword for impedance control; etching accuracy drops, and an experienced thick copper PCB manufacturer must calculate line width compensation tightly. I have seen a board using 3oz copper on an inner layer whose differential impedance was off by nearly 8%, and in the end it had to be re-prototyped, delaying the whole project by two months.<\/p>

Power Noise, Embedded Capacitance and Reference Clock Phase Noise<\/h2>

Now consider power noise. A protocol like CXL is extremely sensitive to jitter, and if the phase noise of the reference clock is even slightly poor, link training may fail. Therefore the power planes feeding the PLL and SerDes can no longer use traditional splitting in layout. More and more people tend to look for HDI PCB manufacturers that can integrate embedded capacitance processes, using very thin dielectric between power and ground layers to form a planar capacitor effect that suppresses high-frequency noise. The stackup design of such a board must be involved from the simulation stage, and changing any parameter later is a major operation.<\/p>

The Latency Chain and Why PCB Cannot Be Considered in Isolation<\/h2>

In the latency chain, besides the processing overhead of the chip itself, the contribution of board-level interconnect is actually larger than imagined. Add the few dozen nanoseconds consumed inside the controller by the CXL mem protocol, then stack on the PCB traces, connectors and the whole physical path through to the peer memory expansion card, and it easily eats up a large tens of picoseconds or so. So for this kind of solution, you simply cannot look at the PCB in isolation; it has to be weighed as part of the whole memory subsystem. This is also why I am particularly cautious now in choosing a high speed PCB manufacturer: I look at whether they have the capability to extract S-parameters for the full path and whether they have measured backplane consistency test reports, rather than accepting boards on the strength of a single impedance test coupon.<\/p>

At the end of the day, CXL will force the PCB industry to become more specialized. In the past an ordinary multilayer board factory could take a high-speed order too, but now projects involving CXL cannot be handled by anyone who does not understand signal integrity or the frequency characteristics of material Dk and Df. For system designers, binding with a capable supplier early and settling the stackup, copper thickness and via design before layout is ten times better than remedial work afterward. Latency in memory interconnect is life itself, and for every fraction of a second in that life, the board cannot be excused.<\/p>

Practical Supplier Collaboration for CXL Hardware Accelerator and Memory Cards<\/h2>

After so many years in high-speed digital circuits, I find that many people, once they talk about CXL, bore into the dead end of the latency budget and cannot get out. A few picoseconds of trace delay is nothing; the bottleneck of the whole link is clearly stuck at the physical implementation layer. Once you have actually drawn a CXL Interconnect PCB, you know that dealing with an HDI PCB supplier, choosing what stack construction and how to handle those few differential pairs, is much more practical than agonizing over a theoretical nanosecond-level budget.<\/p>

I have worked with several multilayer PCB manufacturers, some doing HDI and some specializing in multilayer volume production. Routing CXL is not just drawing connections. When a PAM4 signal passes a connector, that bit of impedance discontinuity is far more deadly than all the board-level propagation delay you calculate. My habit is to compress the traces coming out of the SerDes to the shortest and go straight into the retimer, preferring a cramped board over detouring for equal-length routing just for tidy layer jumps. The corners created by length-matching serpentines introduce phase errors that simply cannot be hidden at a 32G baud rate. Many high speed PCB manufacturers will suggest adding backdrilling, but inaccurate backdrill depth causes stub resonance, so I later preferred a manufacturer capable of third-order HDI, using microvias drilled all the way to completely remove that useless section of copper.<\/p>

Heavy Copper Debate and Power Architecture on Accelerator Cards<\/h2>

The heavy copper debate is also big. On a CXL accelerator or memory expansion card, the ASIC core current easily reaches hundreds of amps, and heat dissipation and voltage drop both depend on thick copper. Once, when I drew a CXL memory pool board using ordinary 2oz copper, the board edge visibly overheated at full load, and voltage sag made the PLL lose lock. Afterwards I had a heavy copper PCB supplier remake the board at 4oz, replacing the whole power layers with thick copper, while completely separating the copper of the digital core from the SerDes power layer, and pressing the ground layers together with embedded capacitance material. After that, the temperature rise dropped by nearly 20 degrees. So now, when I talk about PCBs with anyone, I first ask whether the other side has reliable thick copper PCB manufacturer resources, and latency simulation comes after.<\/p>

Memory Routing, TDR Coupons and Low-Loss Material Choices<\/h2>

The memory side is even more trivial. A CXL Type-3 controller sits next to local DDR5 chips, and that 64-bit parallel bus running at 5600MT suffers speed reductions as soon as crosstalk between traces grows. If you draw by the JEDEC reference layout, many multilayer PCB suppliers will quietly adjust line width and spacing in the actual board to match their etching tolerances, and the impedance ends up off by more than ten ohms. I learned my lesson: every time before releasing boards, I have the multilayer PCB manufacturer produce a real impedance test coupon, measure it with TDR myself when it comes back, and redo it if the data does not match. Spending that time is much faster than getting boards and hunting for the cause when speed will not come up.<\/p>

Some people also agonize over whether to use two stages of retimers, but I would rather spend more on PCB material selection. For a low-loss laminate such as Megtron 7 or IT-968, just confirm the lead time with a mainstream HDI PCB manufacturer and use it directly. With smaller signal attenuation, the number of retimer stages naturally decreases, saving power and one more stage of processing latency. In fact, for CXL memory to approach NUMA-level access latency, the bottleneck is not the propagation delay of one or two nanoseconds in the SerDes channel but the large amount of pipeline overhead inside the memory controller doing address translation and hot page migration. So at PCB level I put more emphasis on leaving enough routing space for the controller’s local DDR channels, using the process of a thick copper PCB manufacturer to hold supply ripple within 20mV, and completely separating the supply of the SRAM holding the tracking tables from the core logic supply. This kind of power architecture split is worth more effort than agonizing over routing differential lines 2mm shorter.<\/p>\t\t\t\t\t\t\t\t<\/div>\n\t\t\t\t

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Why the Factory Partnership Matters More Than New Design Theory<\/h2>

At the end of the day, what this field lacks most is not new design theory but a factory that cooperates closely with you. If you build CXL hardware accelerator cards, you need a supplier that can handle high-speed SerDes routing and heavy copper power layers at once. It must understand the impedance control of a high speed PCB manufacturer<\/a> and also deliver the large-current solutions of a heavy copper PCB supplier. Otherwise, however well you draw, if the board factory’s process falters, all your timing and latency budgets are castles in the air. Anyone who has done real projects should feel this deeply.<\/p>

Why FEC and Protocol Features Cannot Fix the Physical Layer<\/h2>

If the board is not done well, the most advanced protocol is useless. CXL has been on fire for the past two years, and concepts like memory pooling and disaggregation are dazzling, but once they land on a PCB, many teams still hard-carry with old thinking. After hitting walls in several projects, I slowly realized that CXL interconnect’s demand on the physical layer is not as simple as doubling the rate.<\/p>

Take FEC as an example. Many people think that if link quality is poor, forward error correction can carry it through, but the reality is the opposite. FEC can only help clean up the battlefield after your channel has reached a certain threshold; it cannot rebuild order for you. I encountered a 64GT\/s design where impedance continuity was off by a notch and via stubs had not been dealt with cleanly. When the bit error rate went up, FEC simply failed, and training would not pass no matter what. That board was later reworked by a different multilayer board supplier, with backdrill depth controlled within 75 microns and differential pair length matching redone, and only then was link training barely stabilized. It made me fully understand that physical layer pits cannot be filled by the protocol layer.<\/p>

Which Factories Can Build CXL-Grade Boards<\/h2>

Speaking of board factories, after dealing with them these years, there really are not many that can do CXL-grade boards well. Although many manufacturers are labeled as able to make high-speed PCBs, when it comes to PAM4 signals above 32GT\/s, the gap in process shows up instantly. I generally look first at their dielectric material loss and glass cloth selection, and at whether ultra-low-loss materials were used correctly and to what extent residual copper rate is controlled; a few questions on those details screen out more than half. Later I even settled on one or two HDI board factories for long-term cooperation, because they have experience with microvia copper filling and stacked via structures, and signal integrity is thereby assured. Put plainly, for a CXL Interconnect PCB, multilayer board manufacturing capability is hard currency, and choosing the wrong supplier leaves landmines everywhere afterward.<\/p>

Power Consumption, Thermal Management and Heavy Copper Verification<\/h2>

Power consumption is also an easily underestimated link. A CXL Type-3 device does not look outrageous in its power figures, but once it is made into a board-level product, thermal management becomes complicated. A memory expansion module, with a controller plus DDR5 modules, easily consumes more than 20 watts overall, all squeezed into limited space. I encountered a case of thermal mismatch where copper foil current carrying was insufficient and local temperature rise pushed the controller to the edge of throttling. Later we changed to a thick copper board, raised the power layer copper thickness to 3 ounces, and enlarged the cross-section of the thermal channel, and things improved. So now, for any design involving high-density, high-current requirements, I almost always look for a factory that can make thick copper boards stably, whether called a heavy copper PCB supplier or a thick copper PCB manufacturer. The key is their copper thickness uniformity and interlayer bonding force test data, and I would not dare trust any of it without seeing the report with my own eyes.<\/p>

What Must Be Right at Board Level for CXL to Reach Production<\/h2>

Looking back, for the CXL road to truly land, controllers and protocol evolution are far from enough. Every board-level detail, from stackup arrangement to copper foil weight, from HDI process to high-speed signal routing constraints, subtly decides whether a solution reaches mass production or stays on paper. Some teams think a cheap multilayer PCB supplier can handle it, and only when link training fails repeatedly, or ripple on the power supply under full load is large enough to make memory error-correct like crazy, do they realize they boarded the wrong ship. My own experience is that for this class of boards, you must find the right high speed PCB manufacturer at the prototype stage, and even evaluate HDI and thick copper processes together, rather than patching things everywhere late in the project, where the cost is outrageously high.<\/p>

Thermal Vias, Warpage and the Limits of Adding Layers<\/h2>

In CXL expansion card projects, most people at first put all their attention on chip selection, thinking that once the controller is chosen, the rest is just routing. But after several rounds of prototyping, I slowly realized that the choice of board factory is sometimes more of a headache than the chip itself. I once received a board claimed to be capable of high-density interconnect, but its thermal vias were drilled irregularly and the board warped once the copper was thickened, and by the third round of testing the controller overheated and throttled. At such moments you realize that for a reliable HDI PCB manufacturer, being good at stackup and fine line width is far from enough.<\/p>

Looking back now, the real difficulty of a CXL Interconnect PCB is not in signal integrity simulation at all but in how to draw tens of watts of heat steadily out of a flip-chip packaged controller while ensuring the ripple on the several DDR5 voltage rails does not bring the SerDes off course. Some people like to superstitiously believe that stacking up the layer count solves the problem, but in my experience, if the multilayer PCB manufacturer you chose does not even understand copper thickness distribution and power layer partitioning, more layers only means more engineering fees charged. Later I switched to a factory with more experience in heavy copper processes. It was still just a multilayer PCB supplier, but clearly had a better grip on stress relief and via filling in thick copper regions, and it stabilized in three revisions.<\/p>

Splitting Power Rails and Thick Copper in Conversion Areas<\/h2>

I also paid quite a bit of tuition on the power side. Early on, to save cost, the controller’s core supply and the SerDes analog supply used the same DCDC output, and however careful the decoupling, it could not suppress that high-frequency noise. When the eye cannot open, you even suspect your own routing was ruined. In fact, many times the power scheme was just too perfunctory. Now I habitually have the board factory directly make 2oz or even 3oz thick copper in power conversion areas, and find a manufacturer that can produce heavy copper PCB in batches to control the area and impedance of the switching loop, which is much more effective than simply piling on capacitors. When making this kind of board, a thick copper PCB manufacturer often understands your thermal anxiety better than factories that only excel at light, thin HDI; to put it plainly, adding a dozen more microns of heat-dissipating copper is often more direct than changing the fin direction of a heat sink.<\/p>

I will also say something unpleasant: do not expect an HDI PCB supplier that only does quick-turn prototyping to handle this kind of design. Once local heat density comes up, without targeted planning of power and ground planes and copper thickness gradient treatment, yield becomes very ugly with only conventional high-density interconnect. When I get a stackup recommendation from a high speed PCB manufacturer now, the first thing I look at is not differential impedance but how it handles copper thickness distribution on power and ground layers and whether enough current-carrying capacity has been left on high-current paths. That determines how smooth all your later debugging is, and it is more real than any theoretical derivation.<\/p>

Rethinking Bandwidth Drops and Board-Level Physical Domains<\/h2>

When we built the CXL expansion board, our team basically threw all the inertia of prior high-speed digital work into it, and the link bandwidth would never fully reach its target. It was not that it never reached full; it was that it sometimes did, but under long stress testing speed dropped and error rates climbed. At first we circled around the chip, tuning SerDes parameters and swapping firmware versions, and spent two weeks with little progress. Only when we put the board under the microscope for cross-section did we realize that the root cause was not on the silicon side at all; our understanding of a board was simply outdated.<\/p>

Previously, when we worked on PCIe 5.0, boards from the same multilayer PCB manufacturer never had such a mishap, so we naturally assumed that CXL was merely a different protocol layer and the physical layer could continue unchanged. CXL 2.0 on NRZ could still muddle along, but with the PAM4 3.x versions all that complacency shattered. It is not enough that differential pair length matching is controlled; impedance fluctuations and stubs alone can smear your eye into a thin line. In our retrospective, we found that the so-called high speed PCB manufacturer we used before still held CXL Interconnect PCB precision to the tolerance mindset of the Gen5 or even Gen4 era, and copper thickness uniformity and batch drift of dielectric Dk, which are minor, become real bit errors under PAM4.<\/p>

Changing Suppliers and Adopting Any-Layer HDI<\/h2>

Changing suppliers was a decision made through gritted teeth. We found a multilayer PCB supplier that truly does precision lamination of 20 layers or more, with TDR impedance scans running directly on the production line and every board archived. That alone screened out the old channels of good-enough suppliers. For the middle layers that need extremely fine line spacing for BGA fan-out, the stub length of conventional through-hole processes simply could not be held down, so we went to an any-layer interconnect HDI solution. We then contacted an HDI PCB manufacturer specializing in communications backplanes, whose stackup was first back-calculated several versions from the loss budget we proposed, and in the end return loss at differential line corners was also made an acceptance item. These practices used to be fussed over only in RF subsystems, and applying them to a purely digital CXL board was a cognitive upgrade.<\/p>

Heavy Copper Power, Dynamic Response and Thermal Behavior<\/h2>

However, even if the high-speed signal link is arranged smoothly, if the power supply side is not thought through, actual bandwidth still cannot hold up. When a CXL controller and DDR5 chips need to run at the same time, the current demand is a hybrid of steep pulses superimposed on continuous high duty cycles. Our board originally used conventional-copper power layers, and under heavy load the core voltage droop curve showed an obvious low-frequency wobble that directly affected SerDes PLL jitter. Later we gritted our teeth and switched to a heavy copper PCB manufacturer, making all inner power and ground planes 6oz, with local areas on the surface plated up to roughly 10oz as low-resistance paths. In the middle of this you must find a knowledgeable thick copper PCB manufacturer, because interlayer registration and resin filling of thick copper layers are another set of process thresholds, and if lamination shifts even slightly, an inner-layer short means the whole batch is scrapped. The heavy copper PCB supplier I worked with had supplied copper-base boards for automotive power modules, and they had a whole set of rule-of-thumb methods for copper thickness uniformity and embedded copper block heat dissipation; borrowing them was what steadied the tail of the high-current dynamic response.<\/p>

The link and bandwidth issue is ultimately the superposition of the marginal behavior of each physical domain on one board. Many people underestimate the role of temperature in it. One batch of our boards looked beautiful in the test room, where the air conditioning was strong. Placed into a customer’s chassis right next to a GPU array, with the exhaust temperature rising, the CDR lock of the retimer began to drift, DDR5 speed was forced to downshift, and the negotiated CXL bandwidth slid from 32GT\/s to 16GT\/s, so the advantage of memory expansion vanished instantly. If you rely only on the chip junction temperature read by the BMC to adjust fan speed, by the time you react, the link has already oscillated. Later we embedded several thermocouples in the board, leaving one pad each near the connector area and between the memory chips, and fed the real temperature data to the baseboard management unit for predictive handling. There is no ready reference for this; it is a conditioned reflex gained in exchange for burning out a dozen engineering boards.<\/p>

So looking back, CXL expansion is not just a matter of fully absorbing the standard. The intuition from board-level practice is built up together with a reliable HDI PCB supplier and a manufacturer willing to tackle thick copper processes. Some teams, to save cost, want to use a simple redriver instead of a retimer; the link budget looks barely sufficient, but once the extra jitter of a real environment is added, the bit error probability immediately eats the theoretical margin.<\/p>

Why Laminate Grade Alone Does Not Make a CXL Channel<\/h2>

I have been working on CXL memory expansion boards for a while and have stepped on enough pits to write a booklet. At first I superstitiously believed in laminates, thinking that as long as I used ultra-low-loss M8-grade material, longer traces would not be a worry. A later project completely changed my mind. It was a 15-inch board using exactly M8 plus HVLP copper foil, and in theory insertion loss should have been beautiful, yet the eye would not open and latency soared beyond viewing. The investigation traced the culprits to the stub in the connector section and the casual antipad design in the BGA area vias. CXL is different from earlier serial protocols: it holds end-to-end channel budgets tight, and those few dozen nanoseconds of latency directly affect memory access efficiency, which is more troublesome than plain signal loss.<\/p>

So when I choose a multilayer PCB manufacturer now, I look not only at its material library but also care about whether it can control stackup symmetry and whether it has experience making CXL Interconnect PCBs with more than 16 layers. Some factories that bill themselves as high speed PCB manufacturers handle even the reference plane switches of routing carelessly, and their simulation models are full of assumptions. I prefer working with manufacturers who truly understand heavy copper processes, for example having a heavy copper PCB supplier<\/a> make power layers with more than 3oz of copper, so that under high load the voltage drop of the whole board does not eat the DDR5 margin. Sometimes I even ask a thick copper PCB manufacturer to prototype the power layer separately, just to verify the real influence of copper thickness on ripple and thermal distribution. These details matter much more than the laminate model.<\/p>

Power Plane Impedance, Stacked Microvias and Choosing the Right HDI Supplier<\/h2>

Speaking of latency, many people only stare at the signal path and ignore the response time of board-level power delivery. A CXL controller has large transient current, and if the power plane impedance is too high, the recovery time caused by dynamic voltage drop also adds into total latency. I understood this only after suffering badly on a cascaded topology. So now when I look for an HDI PCB supplier, I always ask about their laser blind via filling process and whether they can do stacked vias at 0.5mm pitch, because high-density routing areas often need HDI to straighten out 32GHz signals. If a multilayer PCB supplier pats its chest and says it can do HDI, but stammers when asked about the microvia aspect ratio, I turn around and leave. In short, do not treat laminates as a cure-all; routing topology and power architecture are what decide whether a CXL link can run steadily.<\/p>

Board-Level Process Decides Whether CXL Delivers Its Nanosecond Latency Promise<\/h2>

Over the past two years working on CXL memory expansion in data centers, I have gradually realized something I did not pay attention to before: the choice of PCB base material and process often affects final power consumption and latency performance more than the switch chip itself. Many people start by staring at the CXL controller’s parameter sheet and computing its few-dozen-nanosecond request-response latency, but forget that after the signal leaves the chip package it still has to run several inches on the board. Even if you use a controller claimed to be extremely low-latency, if the trace impedance continuity is poor and via stubs are not handled well, the jitter of those few differential pairs alone is enough to make you suffer.<\/p>

I handled one prototype of a CXL Interconnect PCB from a multilayer board supplier we usually work with, but the first batch of boards could not open the eye when running PAM4 at full rate, and measured latency was nearly thirty nanoseconds more than simulated. Troubleshooting ended at the finding that it was not the schematic that was wrong; dielectric thickness tolerance was too large, and the glass weave effect pushed intra-pair skew beyond expectation. That is when you discover how important a truly reliable multilayer PCB manufacturer is: they must not only control trace width and spacing but also understand the dielectric uniformity of high-speed differential pairs and be willing to check the stackup with you repeatedly. Later we switched to a manufacturer that specializes in high-speed boards, directly used NE-glass base material, and held backdrill depth tolerance within plus or minus 2 mil, and the problem was finally settled.<\/p>

This also made me rethink the usefulness of the thick copper process. The on-board power consumption of a CXL Type-3 module is not small, and once the current density of the controller plus DDR5 comes up, ordinary copper thickness easily causes excessive IR drop on the power planes. We later used 3oz copper locally in the power layers, making the whole board a hybrid structure. That tests the manufacturer’s capability, because not every heavy copper PCB supplier can smooth the transition between thick and thin copper; if interlayer registration is off even slightly during lamination, the impedance of the whole stack drifts. I compared cross-sections from several thick copper PCB manufacturers, and the difference in level is truly large: some have transition sections at the board edge with visible stair steps, and such boards cannot withstand long-term thermal cycling reliability. So the multilayer PCB supplier we eventually chose was selected mainly because they were willing to apply process compensation specifically for high-speed signal areas in thick copper etching accuracy and dielectric filling.<\/p>

Connector Pad Optimization and Why Experienced HDI Suppliers Matter<\/h2>

Another easily overlooked point is impedance optimization of the connector pad area. Many people think the connector is a standard part and copy the reference design, but if you look with TDR, the impedance dip in that transition region may directly pull the return loss of your whole link down by several dB. On our CXL board we locally hollowed out the connector pads and adjusted reference planes, which came out of several rounds of repeated prototyping with an HDI PCB manufacturer. Sometimes you even need to use an any-layer interconnect HDI structure, making signal vias smaller and reducing stubs. That is when you understand why finding an HDI PCB supplier with rich high-speed experience is much more important than simply comparing prices. They can tell you in the design phase which stackup schemes avoid the glass weave effect and which backdrill depth tolerances their production lines can truly achieve.<\/p>

Closing Perspective: Process Engineering Is a Precondition for CXL System Performance<\/h2>

At the end of the day, the physical layer challenge of CXL is that it makes the balance between latency and power extremely sensitive. You cannot make the processor round-trip latency low, so every picosecond of signal deviation on the board has to be fought back; the thermal boundary of a Type-3 module is plain to see, so the design of copper thickness and power integrity must count every penny. For hardware engineers working in this direction, spending more time early on discussing stackup and process windows with a high speed PCB manufacturer is far more economical than staring helplessly at a failed board later. I have stepped on many pits to understand this: board-level process is not a back-end issue; it is a precondition for whether CXL can truly deliver its nanosecond-level latency promises at the system level.<\/p>\t\t\t\t\t\t\t\t<\/div>\n\t\t\t\t

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\n What kind of PCB manufacturer is needed for a CXL Interconnect PCB? <\/h3>\n <\/div>\n
\n A CXL Interconnect PCB needs a manufacturer that can handle low-loss laminates, tight impedance tolerance, controlled backdrilling and HDI microvias together with heavy copper power layers. Few factories can do both in one plant, so many teams evaluate HDI and thick copper capability together or split the design into a signal daughter card and a heavy copper base board. <\/div>\n <\/div>\n
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\n Why is copper foil roughness important for CXL boards? <\/h3>\n <\/div>\n
\n At 32GHz the skin depth is very small, so surface roughness of the copper foil becomes a real source of insertion loss. Datasheet loss values are usually measured before lamination, so finished-board loss must be verified with measured S-parameters, and peel strength must be checked alongside roughness. <\/div>\n <\/div>\n
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\n Do I need heavy copper on a CXL Type-3 memory expansion board? <\/h3>\n <\/div>\n
\n In many designs, yes. Controller and DDR5 current density can cause large IR drop and hot spots with ordinary copper, and inner-layer heavy copper such as 3oz or 4oz helps both current carrying and heat spreading, provided signal layers stay on thin, low-loss copper and the transition between copper weights is well controlled. <\/div>\n <\/div>\n
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\n Should I use retimers or improve the PCB channel first? <\/h3>\n <\/div>\n
\n Improve the channel first. Each retimer adds nearly ten nanoseconds of latency, and a better stackup, lower-loss material, shorter stubs and clean clock routing can often remove retimers entirely. Signal-conditioning devices should be discussed only after PCB process quality, confirmed by TDR reports, is established. <\/div>\n <\/div>\n