A Few NPU PCBs I Built Ended Up Scrapped, and Only Then Did I Learn How to Choose a Board Factory

Wide-Temperature Reliability for Industrial Edge NPU Boards

In the early years I did an industrial control gateway whose main controller used an edge NPU; it was enough for inference and the power consumption could be held down, but the moment the prototype came back it gave me a lesson. The problem was all on the PCB, not any complicated signal integrity collapse, but the most basic cracking of solder joints after thermal cycling. That was when I realized that choosing an NPU PCB is not a matter of finding a multilayer board factory that can route 0.4mm pitch and calling it done.

Let me talk about something practical. Many people think: an NPU, well, just follow the digital board routine, find a factory that can do HDI, stack 10 or 12 layers, with line width and spacing in abundance, and everything is fine. But the pits I have fallen into tell me that the real lifeline in wide-temperature scenarios is the coordination of the lamination structure and the copper thickness distribution. Industrial edge devices hang on outdoor poles all year; they freeze at -30℃ overnight and the enclosure can soar to 70℃ under the sun in the daytime. If this board merely copies the reference design of an ordinary consumer-grade NPU, the stress points of its microvias and buried vias will show you in half a year. My first batch rework was precisely because of a so-called HDI PCB manufacturer that, following conventional HDI, placed all the laser holes directly beneath the BGA pads; after several rounds of alternating hot and cold pulling, the copper at the microvia corners simply fatigued and broke, and when the oscilloscope captured the waveform it was all sporadic packet loss, and it took a full two weeks of investigation before we suspected the physical layer.

Afterward I added a hard line to the requirement sheet: wide temperature must come with a temperature cycling test report. Not the kind where the board factory runs a bare board in a thermal chamber, but one with devices fully assembled, running -40°C to 85°C for at least 500 cycles in actual working state. Multilayer PCB suppliers that can meet this condition are actually not many; once many factories hear that they need a cycling chamber and running under load, their pitch immediately turns to “we make consumer electronics board material, and we suggest medium-loss FR-4 is enough for you.” Whether it is enough you still have to judge yourself, and I look at whether they have a track record in heavy copper processes. Why bring up heavy copper? Because an edge NPU in a compact enclosure conducts 25W of heat through four layers of through-hole copper foil to the heat sink; if the inner layers use only 1oz copper, thermal resistance goes up and the chip’s junction temperature runs out of control. At that point you will find that a truly reliable heavy copper PCB manufacturer will tell you a hybrid solution of inner-layer 2oz plus local thick copper plating on the outer layer, whereas a quick-turn shop that only makes light-copper HDI cannot understand at all why you want to pack multiple layers of 2oz copper onto a board only 0.8mm thin.

There is a very subtle screening logic here. When choosing a multilayer PCB manufacturer, I do not look at how many shiny certifications they have, but first ask one question: how do you manage the compensation factor for inner layers with mixed thick and thin copper during line etching? Those who cannot answer can probably only make standard boards with uniform copper thickness. I have seen a high speed PCB manufacturer that had switched over from high-frequency boards. Its process foundation was fine, but for a mixed-signal board like an NPU it started by piling on M8-grade ultra-low-loss material, and the result was impedance controlled beautifully, but once it was baked in the wide-temperature test, the Z-axis expansion coefficient pulled apart several buried vias. The analysis later showed it had overlooked the large difference in copper fill rate between the digital and analog areas of the NPU board and had not done differentiated lamination stress relief. That lesson was expensive and also made me remember: do not be dazzled by the parameters of ultra-low-loss laminates; the reliability ceiling of an NPU PCB often lies in thermo-mechanical stability, not in those few tenths of a dB of insertion loss.

Now when I place boards, I deliberately give priority to two kinds of manufacturers. One has a background as a heavy copper PCB supplier; they have a natural sensitivity to thermal stress and copper thickness matching, and even if the NPU board’s power layer only uses conventional copper thickness, their experience in interlayer registration and lamination consistency is far better than a pure digital board factory. The other is an HDI PCB supplier that has supplied automotive radar; although they quote a bit higher, their understanding of microvia failure modes is carved into their yield reports. I have a rough screening process on my side: first have the candidate multilayer PCB supplier bring cross-section reports of thick, high-layer-count boards they have built before, pick the microvia cross-section and look at the uniformity of the columnar grains of the copper plating; if there is obvious grain refinement or voids at the corners, basically pass, and do not discuss anything further. This method has no “authoritative standard” behind it, but it works, and it has helped me avoid at least three major customer complaints.

In the end, an NPU PCB is not an isolated technical item; it is a product of the coupling of three physical fields, heat, electricity and force, in board-level space. If you treat the board factory as a partner with whom you can talk about process parameters, rather than simply an order window, some pits have a chance of being exposed before prototyping.

Edge NPU Versus Data Center Thinking: Avoid Over-Specifying

In my years working on edge AI inference devices, my deepest feeling is that too many people have been led by the data center playbook in board-level design. Especially when you first touch NPUs, it is very easy to go directly to a multilayer PCB manufacturer that builds boards for TPUs or high-end GPUs, stack up to 14 or even 16 layers right away, and pull copper thickness to 3oz or 4oz, sending cost flying. Later I found it was not that the tune was wrong, but that even the instrument was chosen wrong. Looked at another way, the transient current of an edge NPU is indeed fierce, but it is a nanosecond-level spike, and the sustained power is far lower than that of a training card, so the key is actually the impedance of the PDN, not the brute-force stacking of copper by a heavy copper PCB manufacturer. Later I found a high speed PCB manufacturer focused on high-speed digital boards, re-evaluated the stackup, reduced 14 layers to 8, used only 2oz copper on the power layers but strictly controlled plane resonance and the placement of decoupling capacitors, and the effect was actually better and the board volume also shrank.

There is a pit that is very easy to step into here: blindly pursuing the HDI order. An NPU is not like a TPU that must fight around the 0.4mm-pitch pads of HBM to assemble third-order or even any-layer interconnect; an edge inference chip’s own pin pitch is not that extreme, and although the LPDDR routing is dense, first- or second-order HDI is enough for fan-out. I have dealt with several HDI PCB manufacturers who habitually recommend more aggressive processes because that is where their profit lies. But you need to tell them clearly that your board does not need to pay for the 55-micron line width and spacing of HBM. The HDI PCB supplier I later settled on understood this very well. After looking at my pin map and stackup requirements, they directly suggested a 2+N+2 structure, which cut cost by nearly forty percent, and signal integrity had no problem. This kind of supplier knows how to use laser holes in busy zones and mechanical buried vias in non-busy zones, rather than stacking microvias across the whole board from the start.

Layer count of a multilayer board is also not “the fewer the better”; it gets stuck on the routing density of LPDDR. I once did a 4-channel LPDDR5X solution, and at first tried to route it on a 6-layer board, and the result was that the address-line topology could never be tuned evenly and the eye would not open. Later I communicated again with the multilayer PCB supplier, and they changed the third layer into a complete ground plane, with signals running on the surface layer and the fifth layer. Although it cost a bit more, the timing margin immediately came up. This experience made me realize that the design constraints of an edge NPU PCB are not benchmarked against a TPU’s SerDes channel count or a GPU’s memory bit width, but against the BGA fan-out method of this very NPU and the temperament of its memory controller physical interface. If you translate the data center formula of “higher layer count, thicker copper, colder plate” directly, either the board’s thermal simulation cannot pass certification or the volume cost simply cannot be sustained.

Speaking of thermal design, this is another disaster zone of wishful thinking. Liquid cooling in edge devices is basically a false need; I have seen someone put a vapor chamber on a 15W NPU, which is pure waste. But going to the other extreme, relying entirely on passive cooling, also easily fails in burst scenarios. In the end we used a 4oz copper base board provided by a heavy copper PCB supplier locally on the board, only in the small area of the Vcore power supply, with standard copper thickness elsewhere, so that it could withstand transient thermal surges without letting the weight and cost of the whole board get out of control. The PCB factory at first did not understand why we did not just thicken the whole board, but after we communicated clearly they actually felt this approach was more reasonable and later even recommended it to other customers as a reference solution.

Many people ask me whether NPU cards will also need HBM in the future. At least on the edge side, I think there is no real demand in sight within three to five years. The memory access pattern of inference tasks is completely different from training; weights are static, and the bandwidth demand of intermediate activations can be fully absorbed by the 6400MT/s of LPDDR5X plus a suitable number of channels. Forcing HBM would not only face the extreme HDI process of the 0.4mm pitch but also push the BOM cost to a number an edge device simply cannot sell at. Even the multilayer PCB manufacturers I have worked with privately admit that the HBM-related PCB orders they receive are almost all training cards and a few high-end inference cards, nothing to do with edge NPUs.

LPDDR5, PCIe Gen4 and Power on One Edge AI Board

After so many years in hardware, I increasingly feel that eighty percent of whether a board can run stably is decided before the schematic is even drawn. Whether the board factory you choose is reliable matters more than the effort you spend later tuning length matching and calculating impedance. Recently I have been following two edge computing projects, both using NPUs, with LPDDR5 on one board, PCIe Gen4 running as well, and sometimes stacking up to 8 or even 10 layers. Anyone with a little experience knows that if you casually find a factory with no feel for high-speed design for this kind of board, once the prototype is powered up the eye closes into a slit, and then the blame is thrown onto the chip’s insufficient driving capability.

I used to make this mistake too, always thinking that following the chip’s layout guide was enough and ignoring the dispersion of board materials and processes. Especially for something like an NPU that easily soars to dozens of TOPS, the instantaneous current variation is even wilder than a GPU’s. Many people are still using the nominal peak TOPS to calculate the power budget, but when the real load runs, a 15-watt burst can kill your PDN design. At that point, if the multilayer PCB supplier in your hands still only knows how to stack copper thickness, it cannot handle dynamic response at all; when the voltage drops into a pit, the compute is directly discounted.

I once tried a board made by a heavy copper PCB manufacturer. I originally wanted to rely on thicker copper to resist large current by brute force, but I had not considered thermal transients, and as a result the solder joints expanded and contracted repeatedly, and intermittent failures appeared in less than half a year. It was instead a board factory specializing as a high speed PCB manufacturer that I found later. They pressed down the PDN loop inductance directly at the stackup stage, and even buried part of the power network directly in the inner layers, saving quite a lot of room for decoupling capacitors. More interesting still, when making an NPU PCB they proactively treat the via escape method under the BGA differently from ordinary logic chips, because an NPU has too many high-speed SerDes and memory interfaces crowded in the same fan-out area, and if you use the traditional HDI laser-blind-via stacking scheme it is easy to squeeze the traces into a dead end.

Many friends who work on embedded systems have asked me what to watch for when choosing an HDI PCB manufacturer. My view may be a bit extreme: do not be fooled right away by words like “can do any-layer interconnect”; look at how they handle the glass fiber effect of the laminate. Some HDI PCB suppliers like to use high-Tg materials, but above 10GHz the loss tangent jumps sharply, leaving the insertion loss margin of PCIe Gen4 tight. I have a machine vision project in hand where the differential lines from the NPU to the camera module were only a little over 4 inches, which by rights was completely within spec, but the first version had excessive jitter because of dielectric dispersion, and in the end I switched to a factory with a measured high-speed laminate database to rein it in.

So now every time a new case comes in, I would rather spend time first flipping through the board factory’s process capability sheet, to see which copper foil type and how many lamination cycles they use, and even to ask clearly how much insertion loss the solder mask has for high-speed signals. Many people do not understand why an edge AI board has more layers than a traditional x86 mainboard; in fact it all goes to the routing of PDN and LPDDR. The LPDDR5X interface of an NPU often uses a 16-bit or 32-bit width, and pressing the length error of all the DQ and DQS groups to within a few ps cannot be done by auto-routing at all; it all depends on people finding space in the stackup, and this is where the experience value of a multilayer PCB manufacturer shows a gap. A good factory will hollow out a section on the reference layer for you in advance and press crosstalk below -40dB, while a poor factory will just ask you to add a shielding can and call it done.

Also, do not think the interconnect of an NPU is simpler than that of a TPU. The torus topology of a TPU looks complex, but at least it has symmetry to follow. With an NPU going PCIe, adding a switch chip at will throws the topology into chaos immediately, and routing multiple differential pairs out of the BGA area without disturbing PDN integrity, while keeping the reference plane continuous, is really not something an average layout engineer can master. I recently ran into a case in which, to save trouble, the layout person simply cut the ground plane in the BGA breakout area, and as a result common-mode noise of two adjacent channels coupled into the RF section and WiFi throughput was halved. After fixing the board, we had to find a multilayer PCB supplier again for a rush build, and the cost doubled.

If you are about to start an NPU project now, I suggest you first get the power curve straight. Do not trust the pretty TOPS/W figure in the material; that is the peak efficiency measured in a lab’s constant-temperature chamber.

Choosing a Fab Early: Power Planes, Heavy Copper and Package Heat

Among the NPU board designs I have handled over the years, there is a rather counterintuitive takeaway: board-level success or failure is often set the moment you decide which multilayer board manufacturer to work with, and after that there is actually not much room to rescue it with simulation and parameter tuning. Many people start by clinging to those few high-speed lines, thinking they are the soul of an NPU PCB, but what really makes the whole board flip is how the power planes are cut and how the loops are routed. Take a core supply from 28V to 0.8V with transients that easily approach a hundred-plus amps: if the HDI PCB manufacturer you find cannot handle the uniformity of blind via copper filling, or if that multilayer board supplier’s lamination registration is off by a dozen microns, the coupling between adjacent power and ground planes in the whole stackup runs off course, and the result is that the PDN impedance curve sprouts a spike at exactly the frequency you need most, and no amount of filtering can remove it.

Another often-underrated issue is the use cases for heavy copper PCB. When many teams hear large current, their instinct is to shout heavy copper. After trying a few times I became cautious instead, especially after several rounds with heavy copper PCB suppliers, where I found that the thick copper accuracy they can guarantee is often concentrated on the outer layers, whereas the inner-layer copper thickness that really determines IR drop, if the process deviation is large, wastes all of your earlier calculated temperature rise and voltage drop. For a while I simply did it the other way around: using finer HDI stacking, I used laser drilling to solder the decoupling capacitors directly onto pads on the back of the chip, cutting the loop by nearly half, and the impedance dropped far more obviously than by just adding thick copper. Board-level heat also became easier to control, because with less loss on the current path, the heat naturally disperses.

Packaging is even more subtle. Now NPUs often integrate high-speed memory inside the package, and on the surface the board-level routing looks cleaner, but once it runs you discover that the center of gravity of the entire temperature field has moved completely from the PCB to the top of the chip. What I remember most is an NPU with a fan-out package, with a whole copper vapor plate under the board, and when the infrared camera looked, the heat was firmly trapped under a small patch of thermal film above the package’s encapsulation layer, and no matter how large the external heat sink, it was useless. At such times, however you switch high speed PCB manufacturers, the little margin of signal integrity is simply not the bottleneck; the whole thermal path has to be derived backward from the package’s mechanical structure to the board-level copper distribution, and board-level design almost becomes an extension of package heat dissipation.

So now when someone asks me how to make an NPU PCB, I generally do not say which design guide to start gnawing on. What I would rather spend time thinking about is how much engineering experience the HDI PCB supplier I choose has in interfacing with package factories, and whether it is willing to bring real process tolerances into the simulation stage and run them together. After all, at this density the board and the chip can no longer be pulled apart, and the pure effort of drawing lines is actually the least worrying part.

Fine-Pitch BGA Fan-Out, 2oz Copper and 6400 MT/s on an Industrial Gateway

After working on edge computing boards for a while, I gradually realized one thing: in the NPU PCB field there are many intimidating concepts, but what really helps you take fewer detours are all lessons paid for with money and time. Staring only at chip compute is useless; as long as the fan-out around the BGA does not go smoothly, the later thermal simulation and signal integrity cannot truly close the loop. One industrial gateway project of ours had an NPU BGA pitch of about 0.5 mm, with board thickness required to be pressed within 1.6 mm, and the layer count could not be too high. When I contacted conventional multilayer PCB manufacturers, their process limit was stuck at mechanical drilling of 0.2 mm holes, and they simply could not make clean through-holes on a 0.4 mm pad. I had no choice but to grit my teeth and find an HDI PCB supplier, who said right away that this density required laser drilling and second- or third-order stacked holes. In the early prototypes the scrapped boards stacked up to nearly half a palm thick; each microvia offset sent the impedance flying, and in those days we spent every day circling cross-section images and X-rays.

After the board ran, another trouble came up. NPU inference has fierce current jumps when the load changes suddenly, and a one-ounce copper power plane could not hold the transient. I tried changing the inner-layer power to thick copper, and at first I was worried that multilayer lamination would leave insufficient resin fill and that more bubbles would directly affect thermal conductivity. A friend recommended a heavy copper PCB supplier, who used vacuum lamination to press 2 oz copper and prepreg quite solidly, and after the thermal shock test the cross-sections showed basically no voids. When I tested the board, after running at full load for a dozen minutes, the area that previously could soar above 90 degrees locally stayed steadily around 75 degrees, which is a fairly big difference in a sealed enclosure with no fan. After that, my team and I became very stubborn about inner-layer copper thickness: for designs with continuous large current, first ask the heavy copper PCB manufacturer whether it can do 2 to 3 oz inner layers, otherwise you are digging a pit for yourself.

The high-speed interface is also a harsh gate. High-speed memory requires strict impedance control of differential pairs and a small length-matching tolerance, and one of our boards was fitted with LPDDR at 6400 MT/s, with a crowded and dense routing area. The stackup proposal given by the multilayer PCB supplier we initially found still used ordinary FR4 prepreg parameters, and when the pilot-run board came back and was measured, the eye collapsed into something unwatchable. We had to switch to a factory that had long worked as a high speed PCB manufacturer, who re-tuned the dielectric thickness and line width according to my differential line model, and in the end the line width was set near 3.2 mil to get the impedance right. This experience directly changed my understanding of board factory process capability: it is not that if the factory can produce an eight-layer board it counts as able to do high speed; the key is the impedance calculation and the control of actual process deviation.

People often ask whether edge NPU boards do not need to be so particular. My feeling is exactly the opposite: precisely because space is tight and heat dissipation means are limited, the fault tolerance of the board-level physical implementation is lower. In the most recent prototype run, for a thin board only a millimeter or so thick, the HDI PCB manufacturer got the solder mask opening accuracy to ±0.02 mm, and the pads under the NPU showed no solder bridging or cold solder, and the yield went up at once. So now when I do a project, even if the schedule is tight, I first talk through the three points of microvias, solder mask and impedance with the HDI PCB manufacturer. What this communication cost buys back is a board that can truly go into production.