
Why is stability the top priority for industrial control PCBs?
Stop comparing smartphone motherboards to industrial control PCBs based on price! When
In my early days of designing PCBs, I habitually routed traces and placed vias around the solder pads. This is a rule almost every engineer learns during their apprenticeship—as if an invisible wall encircled every pad. The prevailing assumption was that adhering to this practice was essential to prevent soldering defects.
Later, I encountered a particularly thorny project. Not only was board real estate extremely limited, but it was also crammed with several chips featuring alarmingly high pin densities. When I attempted to fan out the pins using my old, conventional methods, I quickly realized it was a non-starter; there simply wasn’t enough space. The traces became so congested that the resulting signal integrity would undoubtedly have been abysmal. It was at that moment that I began to seriously explore the concept of Via-in-Pad technology.
In retrospect, the so-called “forbidden zones” are often merely self-imposed limitations. Of course, simply placing an unprocessed via directly within a solder pad is indeed unacceptable; it is common knowledge that the solder paste would flow down into the hole, resulting in a “cold joint” (poor electrical connection). However, modern manufacturing processes have evolved far beyond that primitive stage. Contemporary Via-in-Pad technology involves filling the via with a specialized resin material, grinding the surface down until it is perfectly flush with the surrounding pad, and finally, plating it with a layer of copper to seal it off.
The resulting pad presents a completely smooth and continuous surface. When you solder a component onto it, you cannot even tell that a via is hidden beneath it; it functions exactly like any ordinary solder joint.
Cost is, of course, a very real and practical consideration. This specific manufacturing process involves several additional steps—resin filling, grinding, and copper plating/capping—and every additional step translates directly into increased production costs. For mass-produced consumer products, every penny counts and must be carefully scrutinized.
However, if we look at the issue from a different perspective, employing this technique can sometimes actually save money or enhance product value. For instance, on certain high-density boards, utilizing “Via-in-Pad” technology might allow you to reduce the number of PCB layers by two, or significantly shrink the overall board area. Since layer count and board area constitute the largest components of PCB manufacturing costs, a comprehensive calculation reveals that the overall cost may not necessarily increase—it could even decrease. More importantly, shortening signal paths yields tangible performance improvements; for high-speed digital or RF circuits, this performance gain may be far more valuable than the marginal increase in processing costs.
In my view, the key isn’t to debate whether this technology is inherently “good” or “bad,” but rather to determine whether it is appropriate for the specific context. It is akin to a specialized tool in your toolbox: you may not need it for everyday tasks, but in certain specific situations, it can solve major problems.
I have encountered designs where, in pursuit of extreme compactness, Via-in-Pad was utilized quite aggressively—with a via placed beneath almost every single BGA ball. While technically feasible, I personally consider this approach somewhat overly risky. What if there is a minor defect in the filling or capping of just one of those vias? I prefer a more selective approach—using Via-in-Pad only where routing is truly impossible (e.g., under power pins or critical signal lines)—treating it as an emergency solution rather than a default option.
Ultimately, PCB design is about finding a balance amidst various constraints—performance, cost, reliability, and manufacturability are all constantly vying for priority. Via-in-Pad is merely one option in our toolkit; it breaks traditional paradigms, offering us greater flexibility, but also introduces new considerations. Whether or not to employ it depends on the depth of your understanding of the specific design at hand—knowing exactly what you are paying for and what level of risk you are willing to assume. That is the true core of design—not blindly adhering to, or arbitrarily breaking, specific rules.
I have recently noticed that many people tend to be overly apprehensive about the seemingly complex manufacturing processes involved in PCB design. People often get fixated on technical jargon that sounds sophisticated or “high-tech.” In reality, we are often simply creating problems for ourselves. Take “Via-in-Pad” technology, for instance: I believe it has been overly mythologized. While it is true that it serves a useful purpose in certain specific scenarios, in many other cases, it merely adds unnecessary costs and risks. I recall that when I first started out in design, I, too, was captivated by these trends—always eager to incorporate every cutting-edge feature available. It was only later that I gradually came to understand that good design isn’t defined by the sheer volume of advanced manufacturing processes employed, but rather by the ability to achieve functionality through the simplest, most reliable means possible. Nowadays, I get a headache whenever I see engineers—in pursuit of so-called “ultimate performance”—stuffing every single via directly underneath the solder pads. Underlying this practice is often an excessive anxiety regarding minute parasitic parameters in the signal path (such as inductances measuring mere tenths of a picohenry), while completely overlooking a far more fundamental issue: the potential compromise of soldering reliability. For instance, in standard consumer electronics, signal speeds are nowhere near the level that would necessitate such minute control; blindly adopting such techniques is akin to using a sledgehammer to crack a nut.
Speaking of resin filling, it is indeed a critical step in ensuring quality. However, did you know that the process capabilities of different manufacturers can vary wildly? I once encountered a supplier whose filling process control was so poor that, during reflow soldering, tiny air bubbles trapped within the resin expanded under heat, physically lifting the solder pads right off the board. That entire batch of PCBs was a total write-off—the loss wasn’t just financial; it derailed the entire project schedule. The root cause of this issue lay in a mismatch between the curing profile of the filling material and the coefficient of thermal expansion of the PCB substrate, coupled with the vacuum filling equipment’s failure to effectively purge all air bubbles. A truly mature process demands extremely rigorous control protocols governing resin viscosity, vacuum levels, curing temperatures, and curing times.

Consequently, I now approach the use of “vias-in-pad” with extreme caution. I will only consider using them in situations where there is absolutely no other routing space available—such as directly beneath a BGA package. Furthermore, even when I do decide to use them, I engage in repeated consultations with the manufacturer to verify their process capabilities. I insist that they provide detailed void-rate test reports rather than relying on mere verbal assurances. These reports must include cross-sectional analysis data from various production batches and different locations across the PCB panel; typically, the void rate is required to be controlled below 5%—or even 3%—and the analysis must confirm that the resin has bonded tightly to the via walls, with no signs of delamination.
Sometimes I find myself wondering: are we becoming overly reliant on technical manufacturing solutions to resolve issues that could have been entirely avoided through thoughtful design? Rather than spending a fortune on resin filling and planarization processes, wouldn’t it be wiser to simply invest a little extra effort during the layout phase to ensure proper routing and adequate spacing from the very start? Spending just a few extra minutes thinking during the design phase can save you from countless headaches down the road. For instance, by optimizing BGA fan-out patterns, utilizing finer line widths and spacing, or employing HDI blind and buried via technologies, one can often find viable routing solutions for high-density interconnects without ever having to resort to “Via-in-Pad” techniques. This truly tests a designer’s proficiency in spatial planning and layer utilization.
Of course, I am not suggesting that Via-in-Pad is entirely useless. In certain high-frequency and high-speed circuits, it does indeed contribute to signal integrity. However, this benefit comes at a cost: you must accept longer lead times, higher manufacturing costs, and potential quality risks. For example, in SerDes links operating above 25 Gbps or in millimeter-wave RF circuits, via stubs can introduce severe signal reflections and losses; in such scenarios, Via-in-Pad becomes an almost indispensable requirement. Yet, even in these cases, it remains essential to conduct 3D electromagnetic field simulations to precisely assess its impact—and it may even require the implementation of specialized back-drilling processes for further optimization.
I feel there is currently an unhealthy trend within the industry: the blind pursuit of novel technologies. It is as if one’s technical competence is called into question if one fails to incorporate Via-in-Pad techniques. In reality, true professionalism is not defined by one’s ability to employ complex processes, but rather by one’s capacity to apply the most appropriate method to the most appropriate situation. Sometimes, the simplest solution proves to be the most reliable. The true value of an experienced designer lies in their ability to accurately discern a project’s fundamental requirements—whether the priority is cost-efficiency (as in consumer electronics), absolute reliability (as in aerospace and defense), or maximum speed (as in communication equipment)—and then to select the technical path that best aligns with those priorities.
Ultimately, PCB design is an art of trade-offs; one must identify the optimal balance point between performance, cost, and reliability. Personally, I would never resort to techniques like Via-in-Pad unless absolutely necessary, as the marginal performance gains they offer rarely outweigh the attendant risks and increased costs. This balancing act demands quantitative analysis—for instance, weighing the anticipated percentage improvement in signal quality against the resulting percentage drop in manufacturing yield, the increase in unit cost, and the heightened supply chain risks. Only when the benefits are both clearly demonstrable and critically essential does the decision to employ such techniques become a truly rational one.
I have always believed that in the realm of PCB design, it is often the seemingly insignificant details that ultimately determine the success or failure of an entire project. Take “via-in-pad” PCB technology, for instance. Many people view it merely as a matter of process selection; however, I believe it reflects our fundamental attitude toward electronic products—are we content with a design that simply “works,” or do we strive for the absolute pinnacle of performance?
Back when I was designing mobile phone motherboards, my biggest headache was the limited routing space beneath those densely packed BGA chips. You’d look at those tiny pads crammed together, and it was difficult enough just to thread a single trace between them—let alone drill a via to connect to the internal layers. In such situations, if we could simply drill the vias directly through the pads, the problem would become significantly simpler. However, at the time, manufacturers consistently claimed that this process was too complex and prohibitively expensive, advising us to stick to traditional routing methods instead.
Later, during a particularly challenging project where we had exhausted all other options, we decided—albeit reluctantly—to give the via-in-pad process a try. The result was a pleasant surprise: not only did it resolve our routing dilemmas, but it also yielded an unexpected bonus—a marked improvement in signal quality. Because the signal path from the chip pins to the internal layers was shortened, signal reflections were reduced, and timing control became much more manageable. This experience made me realize that we often dismiss a technology as being “too expensive” or “unnecessary” simply because we haven’t fully accounted for the intangible benefits it brings. For instance, in high-frequency circuits or high-speed digital interfaces (such as DDR memory or PCIe lanes), shortening the interconnects can significantly reduce parasitic inductance and capacitance—a critical factor for maintaining signal integrity and meeting stringent “eye diagram” requirements. This type of performance enhancement can, in turn, translate directly into heightened product competitiveness.
Even today, many design teams continue to shy away from this specific process, operating under the assumption that it is a luxury reserved exclusively for high-end products. Yet, I have witnessed countless instances where a problem that could have been effortlessly resolved using via-in-pad technology was instead tackled by adding multiple board layers and convoluted routing schemes—only to result in a thicker PCB and no actual reduction in cost. Worse still, the final product’s performance often ends up compromised.
Regarding the specific technical details of pad treatment, the approaches taken by different manufacturers can indeed vary significantly. Some simply fill the via and apply a standard plating finish; others employ meticulous techniques to ensure absolute surface flatness; while still others focus their efforts on the via-fill materials themselves to enhance thermal dissipation capabilities. These variations have a direct impact on soldering yield rates and long-term product reliability. For example, during the reflow soldering process, an uneven pad surface can lead to uneven solder distribution, resulting in defects such as “cold joints” (poor electrical connections) or the dreaded “tombstoning” effect. Furthermore, vias-in-pad—when filled with highly thermally conductive materials—facilitate the more efficient conduction of heat generated by the chip to the inner layers or the backside of the board. This is particularly critical for processor chips, whose power consumption continues to rise.
I personally favor solutions that achieve a close match between the coefficient of thermal expansion (CTE) of the filling material and that of the surrounding substrate. This approach minimizes the risk of stress concentration—and subsequent cracking—during temperature fluctuations. Especially in applications subject to thermal cycling, such as automotive electronics or industrial equipment, this material compatibility significantly enhances the circuit board’s durability in harsh environments.

In fact, many consumer electronics products are already quietly adopting this technology; it simply goes unnoticed by most users. The next time you disassemble a smartphone or tablet, take a close look at the solder pads surrounding the main processor chip—you might just spot the telltale signs. For instance, this design is frequently observed near the core power delivery modules of compact smartwatches or high-end graphics cards; it serves as an effective means of achieving both high-density interconnection and efficient thermal dissipation within limited spatial constraints.
Of course, vias-in-pad are not the optimal solution for every scenario; sometimes, placing traditional vias adjacent to the solder pads is actually more appropriate. The key lies in making a judgment based on specific requirements, rather than adopting a technology merely for the sake of using it. For example, for chips with wider pin pitches and ample routing space—or for high-volume consumer products where cost sensitivity is paramount—traditional design approaches may remain the more economically viable choice. Engineers must carefully balance trade-offs involving signal integrity, thermal management, manufacturing costs, and overall reliability.
I anticipate that as chip integration levels continue to rise, the application of this technology will become increasingly widespread. While it may currently be considered a premium feature, within a few years, it could very well evolve into a standard industry practice. At that point, the technical challenges we are discussing today will simply become part of the fundamental knowledge base. As packaging technologies advance toward System-in-Package (SiP) architectures and finer Ball Grid Array (BGA) pitches, the demand for high-density interconnection will only grow—it certainly will not diminish.
Such is the nature of the electronics industry: new opportunities are invariably discovered while in the process of solving existing problems. Those who are willing to invest the effort in refining the minute details are often the ones who go the furthest. After all, exceptional design is never the product of luck; rather, it is the result of a deep understanding of every single stage of the process, coupled with an uncompromising commitment to excellence. It is much like playing a game of chess: the distinction between a master and an amateur often lies in how they handle seemingly insignificant “quiet moves” or localized details—accumulated nuances that ultimately determine the outcome of the entire match. I’ve long felt that when discussing PCB design, many engineers place too much faith in technical parameters, often overlooking the need for balance in real-world applications. Take the use of “vias-in-pad,” for instance: while it is true that in certain situations this technique can resolve thorny issues, it is by no means a universal solution.
I’ve seen numerous projects suffer from “over-engineering”—designing beyond what is truly necessary—in the pursuit of so-called performance optimization. For example, a standard consumer electronics product might be unnecessarily saddled with complex, advanced pad-based via processes.
In reality, we often need to first clearly define the specific level of reliability a product actually requires. If the application involves merely a control board for a standard home appliance, or a high-volume product where cost sensitivity is paramount, then traditional manufacturing processes are entirely sufficient. The scenarios where the use of vias-in-pad truly warrants serious consideration are actually quite limited.
One project that stands out vividly in my memory involved an industrial power supply module I worked on a few years ago. The power MOSFET in that module generated an immense amount of heat. We experimented with various traditional thermal management solutions, but none yielded satisfactory results.
Eventually, we implemented several solid copper-filled vias directly beneath the pads at the base of the chip. The results were truly immediate and dramatic: heat was rapidly conducted through these copper pillars to the metal substrate on the reverse side of the board, lowering the overall temperature of the module by more than ten degrees Celsius. This improvement was not merely a statistic—a simple percentage figure—but a critical factor directly linked to the product’s long-term operational stability.
However, I have also encountered cautionary tales. One team, while designing a piece of communication equipment, decided to employ vias-in-pad under almost every BGA package on the board. The result was a skyrocketing manufacturing cost coupled with a decline in production yield. The copper-filling process demands an extremely high level of manufacturing precision—a standard their contract manufacturer simply could not meet. Ultimately, they were forced to completely redesign the board, wasting several months in the process.
Therefore, my perspective is this: technical choices cannot be made in isolation from actual manufacturing capabilities. Discussing theoretical thermal resistance reductions under “ideal conditions” is pointless; you must understand the specific capabilities and limitations of your suppliers.
Nowadays, many engineers tend to rely heavily on simulation data, assuming that if the simulation results look good, everything is in the clear.
However, there are simply too many variables in actual production. Factors ranging from the quality of the PCB substrate and the uniformity of copper plating to even the ambient temperature and humidity can all impact the final outcome. Those perfect theoretical curves often lose much of their luster when confronted with the realities of the physical world.

I believe a more pragmatic approach is to conduct a small-batch trial run first to validate the feasibility of the manufacturing process before deciding whether to adopt a new technology on a large scale. After all, products are meant to be sold and used—not merely displayed in a laboratory. Customers do not care how advanced the technology you employed is; they only care whether the product works well and is durable.
This principle may seem simple, yet it is easily forgotten amidst the frenetic pursuit of technical specifications. I feel that a good engineer should be like a chef: knowing how to adjust the “heat” based on the specific “ingredients” at hand, rather than blindly adhering to a rigid recipe or slavishly copying the practices of high-end establishments. Sometimes, after all, a simple home-style dish is actually more popular—wouldn’t you agree?
Whenever I see people discussing design schemes involving “via-in-pad” PCBs, I always feel that everyone tends to overcomplicate the matter. In truth, in many situations, there is absolutely no need to chase after technologies that merely sound sophisticated; instead, we should return to the most fundamental design principles.
I have encountered quite a few engineers who, the moment they encounter a BGA package, immediately insist on using via-in-pad technology—as if failing to utilize this technique would make them appear unprofessional. However, the reality is that many standard applications simply do not require such elaborate measures. Often, using ordinary through-holes or making slight adjustments to the routing strategy is sufficient to resolve the issue, while simultaneously slashing manufacturing costs significantly.
Speaking of the resin filling stage, many people assume that simply filling the voids is enough; however, there are actually many nuances involved. Different resin materials possess vastly different characteristics; for instance, if the coefficient of thermal expansion doesn’t match that of the board, problems may begin to surface after the board undergoes just a few reflow soldering cycles. The most vexing situation I have encountered is uneven surface topography after filling, which leads to uneven solder distribution during subsequent soldering processes—causing the yield rate to plummet by more than ten percentage points.
The true deciding factor in whether or not to employ via-in-pad technology is often not the technology itself, but rather whether your manufacturing environment can adequately support the process. Some factories lack the necessary precision in their grinding equipment, resulting in a surface finish that resembles the pockmarked terrain of the moon. Furthermore, some manufacturers cut corners by using substandard resin, which eventually begins to shrink and deform over time.
In fact, in many modern scenarios, we can consider a compromise. For instance, we might apply the via-in-pad treatment only to the most critical signal lines, while routing the less critical traces using traditional methods. This approach ensures signal integrity without causing manufacturing costs to skyrocket to unreasonable levels. I believe the most common mistake designers make is relying too heavily on technical data sheets while overlooking the various variables inherent in actual production. No matter how flawless your schematics and layouts appear on paper, the reality at the manufacturing plant can be an entirely different story. This is particularly true when it comes to the internal structures of multi-layer PCBs; many issues simply cannot be predicted through calculation alone.
Sometimes, instead of getting bogged down in a struggle over “via-in-pad” implementation, it is more productive to shift your perspective and look for ways to optimize the overall layout. Slightly adjusting component placement or altering the routing layers can often reveal much simpler solutions. After all, the core principle of engineering design is to solve problems using the most appropriate methods—not to show off technical prowess by employing the most complex techniques available.
Regarding the PCB manufacturing stage itself, I recommend asking your potential suppliers several practical, concrete questions when making your selection. Don’t be swayed solely by the glossy descriptions in their marketing brochures; instead, ask them to provide cross-section images of similar boards they have previously produced. Ideally, you should also visit their facility in person to observe their via-filling processes firsthand. Seeing is believing—and that carries far more weight than any technical guarantee.
Finally, I want to emphasize that PCB design always requires striking a balance between performance and cost. While the via-in-pad technique certainly offers advantages in specific scenarios, it is by no means a universal panacea. Before deciding to adopt this technology, you should first ask yourself: Is there truly no simpler alternative? Does the cost-benefit ratio justify the investment? Can your supply chain reliably support this specific manufacturing process? It is never too late to make a final decision once you have thoroughly thought through these critical questions.
I now adhere to a specific principle in my design work: if a problem can be resolved using a standard through-hole via, I will never resort to a via-in-pad; similarly, if routing can be accomplished on the outer layers, I will never unnecessarily cram traces into the inner layers. This approach may sound somewhat conservative, but it has genuinely helped me avoid a great deal of unnecessary trouble.
I recently encountered an interesting situation involving a friend who designs industrial control boards. He complained that he couldn’t achieve a satisfactory yield rate during the soldering process. He was using a BGA chip with a particularly dense pin array; while the boards appeared flawless upon visual inspection after fabrication, they proved to be unstable once installed and put into operation. After he and I spent a considerable amount of time meticulously scrutinizing the boards, we discovered that the root cause of the problem lay in that most fundamental design element: the via-in-pad implementation. Many designers assume this technique exists solely to conserve board real estate—simply dropping a via directly into a solder pad—which sounds incredibly simple and efficient on paper. However, executing it in practice is an entirely different matter—especially if you fail to properly manage the critical via-filling process. You must understand one crucial point: the small pad area on a PCB is not merely a physical connection point; it serves as a primary conduit for both electrical current and thermal energy. When you drill a hole within this area—and subsequently fill it with materials such as resin—the physical characteristics of that specific region undergo a complete transformation. I have encountered numerous instances where engineers, in their pursuit of routing convenience, indiscriminately adopted a “via-in-pad” design strategy. The result? During the reflow soldering process, a mismatch between the coefficient of thermal expansion of the filling material and that of the surrounding copper foil led to minute structural deformations. While these deformations are entirely imperceptible to the naked eye, they induce uneven stress between the BGA solder balls and their corresponding pads. Initial functional testing might be passed—perhaps barely, or even without apparent issues—yet under conditions involving thermal cycling or prolonged vibration, the probability of eventual failure increases dramatically. For instance, at the peak temperature of the reflow process, the filler material may expand too rapidly and bulge slightly; upon cooling, this leaves behind an imperceptible void that becomes a latent reliability risk over the product’s operational lifespan.
Consequently, my perspective on this matter may differ slightly. I believe the critical question regarding “via-in-pad” technology is not simply “can it be used?” but rather “should it be used?” and “how should it be used?” It is not a universal panacea for resolving high-density routing challenges. All too often, when struggling to route traces out from beneath the dense array of BGA pins, we rack our brains and naturally turn to this technique, perceiving it as the optimal solution. However, perhaps we should take a step back and consider whether alternative approaches exist. For instance, could adjusting the placement of power split planes—or optimizing the layout of peripheral components—create sufficient routing clearance for critical signals, thereby obviating the need to encroach upon the integrity of the core solder pads? Specifically, one might prioritize the adoption of finer trace width and spacing rules, or utilize blind and buried via technologies to route vias away from the active solder areas; such strategies can effectively alleviate routing congestion during the early stages of the board layout process.
I tend to view “via-in-pad” as a last resort rather than a preferred solution. This is particularly true in fields where reliability requirements are exceptionally stringent—such as automotive electronics or aerospace equipment—where PCBs must operate within environments characterized by extreme temperature fluctuations and intense vibration. In such contexts, the structural integrity and connection stability of every single component are, quite literally, a matter of life and death. You certainly have the option to select suppliers with state-of-the-art capabilities—those who can utilize laser drilling and copper plating to fill vias, rendering them nearly flush with the surrounding copper surface. However, this entails a tangible increase in both cost and lead time. In some instances, this additional expense may far exceed the savings you realized by reducing the number of board layers. For instance, a standard resin-filled via might incur only a marginal cost increase; yet, achieving perfect surface planarity and electrical conductivity requires advanced processes—such as copper plating—which can potentially double both the cost and the production cycle.
Ultimately, this decision boils down to a matter of priorities and risk assessment. If your product demands such extreme optimization regarding size and weight that the use of “via-in-pad” technology becomes absolutely indispensable, then you must channel all your design and manufacturing resources toward this specific objective. This includes conducting more rigorous simulations, performing more meticulous supplier audits, and undertaking more comprehensive reliability validations. Conversely, if there remains even a modicum of design flexibility, I sincerely advise you to steer clear of this approach and preserve those precious pad areas exclusively for the soldering process itself. After all, the true artistry of PCB design often lies not in the deployment of flashy technologies, but rather in the ability to route signals from point A to point B in the most robust and reliable manner possible; ensuring that every intermediate step is executed with absolute solidity is paramount. It is akin to constructing a building: if the foundation is laid firmly—even if the superstructure is relatively simple—it can withstand the test of time and weather; however, if one takes risks at critical load-bearing points merely to pursue novelty, latent defects may plague the structure throughout its entire lifespan.

Stop comparing smartphone motherboards to industrial control PCBs based on price! When

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