GPON PCB Design: Can Your Board Actually Hold a Stable Burst-Mode Optical Signal?

APC Loop Design, Op-Amp Selection, and Etching Precision

A lot of people, the moment GPON PCB comes to mind, immediately think about how to route the differential lines nicely and control impedance, then go find the cheapest high frequency PCB manufacturer to have the board built. Designs built with this mindset will most likely stumble at the optical eye diagram, and you will not even be able to find the cause, because the schematic looks perfectly fine.

Over the years working with laser driver circuits, I have increasingly come to feel that APC loop design is a real dividing line. Look at the chip datasheet and it is all drawn out clearly — a back-facet photodiode samples the light, compares it against a target value, and dynamically adjusts bias current — as if closing the loop is enough to stabilize optical power. In reality it is nothing like that simple. That tiny temperature drift on the sampling resistor, at the milliwatt-level of optical power adjustment, can be enough for a temperature swing of just a few degrees to knock your optical module offline in a high-temperature chamber. Not to mention op-amp offset voltage — some low-cost designs use generic op-amps where a drift of a fraction of a millivolt is enough to push the APC loop toward saturation or shut the laser off entirely. I got burned by this, so now I only choose op-amps with Vos under 50 microvolts across the full temperature range — even if it costs a few extra cents, it is cheaper than the rework that follows otherwise.

Another thing that is easy to gloss over is the few centimeters of trace between the laser and the board. Many people think this is just an ordinary analog signal and route it carelessly, only to find the eye diagram either overshooting or with a sluggish rising edge. This is actually parasitic inductance at work — the steeper the driver current, the more that small trace inductance amplifies the signal distortion, sometimes several times over. Reducing this inductance takes more than just careful layout — it also depends on the high frequency PCB supplier’s process capability. Copper thickness tolerance, dielectric layer uniformity, even copper foil surface roughness all directly affect high-frequency loss. I went through three suppliers before settling on one — not the cheapest, but the one using low-roughness reverse-treated copper foil paired with laser direct imaging for trace width, which produced noticeably more consistent boards. With the exact same driver circuit and the exact same laser, switching to this supplier’s board gave us 20% more eye-diagram margin — not something you can make up for by tweaking resistors and capacitors.

So do not treat a GPON PCB like an ordinary digital board. On one side it carries Gbps-level differential data, on the other, sensitive analog feedback, with high-current switching sandwiched in between. Power splitting, ground bounce, and the board material’s Dk and Df variation — concepts you never had to worry about in the low-speed era — become critical here, and even a slight parameter deviation shows up as inexplicable packet loss or optical power drift. Early on, to save time, I let an ordinary PCB shop prototype a board, and when it came back and I tested the APC, the lock time was twice as long as simulation predicted. It took a full week to discover the board material’s dielectric constant varied too much with temperature, causing parasitic capacitance fluctuations on the MPD trace that delayed the sampling signal. From then on, I only work with high frequency PCB manufacturers that have Rogers or similar material experience and can provide frequency-dependent Dk/Df test reports, even if it means waiting a few extra days for delivery. In short, circuit design sets the floor, but the board shop’s process sets the ceiling — and in optical communications, that is not just an empty saying.

Clock Recovery: Why the Reference Clock’s Own Cleanliness Matters More Than the CDR Chip

Back when I was building GPON ONUs, I once got badly burned on a board where the problem traced to clock recovery in the CDR. It was not that the differential lines were poorly routed, and it was not an impedance issue — it was that power supply noise on the reference clock coupled into the PLL loop, causing the CDR’s lock window to drift badly. After that incident, I became almost obsessive about clock cleanliness. Many people think fiber-to-the-home equipment, at only 2.5G downstream, does not count as high speed — but GPON’s continuous downstream data stream and burst-mode upstream place demands on the clock system that are not remotely in the same league.

A clock is not something you can just drop a crystal onto and call it done — it has to withstand interference from every other module on the board, especially since an ONU also packs in Wi-Fi and a voice DSP. If ground bounce or power ripple manages to sneak into the clock buffer, the CDR’s jitter tolerance visibly degrades. When I now lay out a GPON PCB, no matter how short the clock trace is, I treat it like an analog signal — surrounded by ground pour on all sides, with the reference layer below never crossing a split, and I always choose a crystal with phase noise below -150dBc/Hz at a 10kHz offset. Do not believe claims that an SoC’s built-in CDR is robust enough on its own — the underlying physics does not lie. If the reference clock itself already has a period jitter of a dozen picoseconds, no matter how fast the CDR is, it will struggle to lock phase within a few dozen nanoseconds under burst mode, and the upstream packet’s bit error rate will suddenly spike under extreme temperature. Worse, this kind of problem does not show up on a simple room-temperature eye diagram — it usually only emerges when long fiber, high temperature, and weak light stack together, which makes it as hard to find as a needle in a haystack.

On the subject of high-frequency PCBs, I later switched to a high frequency PCB manufacturer specializing in optical communication boards, which finally solved a lingering reflection problem. The previous shop claimed to control 100-ohm differential impedance, but the actual inner-layer copper thickness and dielectric thickness tolerance were too loose, and measured impedance could vary by seven or eight ohms between the board edge and center. The CML differential pair from the optical module to the SoC produced an eye diagram that looked half-asleep. So choosing the right high frequency PCB supplier matters enormously — not every shop that can print traces can actually do this. I now insist on reviewing the supplier’s impedance test reports and confirming they use real TDR measurement rather than just calipers to measure trace width. The board’s dielectric material also has to be locked down — do not use generic FR4 variants, because dielectric constant drift at high frequency shifts differential delay, and the CDR’s clock recovery ends up taking the blame.

There is another easily overlooked detail on the GPON CDR side — the selection of the receive-end AC coupling capacitor. I make a habit of using a 0201-package 100nF capacitor, placed close to the optical module side, with the capacitor’s pad drilled directly to the reference layer rather than dangling off a stub of trace. This reduces reflections caused by parasitic inductance and keeps the burst signal’s edges cleaner. If the board shop does not coordinate closely with the designer on these details, no amount of debugging afterward can save you. So every time I work with a new high frequency PCB supplier, I first prototype a test board specifically to run the eye diagram on the optical interface, confirming they can properly execute my designed differential structure and via stub process before placing a bulk order. At the end of the day, something as seemingly mature as GPON ultimately comes down to how deeply the supply chain understands high-frequency detail.

Case Study: Split Reference Planes and Isolated Power Rails

Over the past several years I have handled quite a few GPON projects, and every time, what gave me the biggest headache was not the schematic design — it was how to safely place high-speed signals and sensitive circuitry together on one board. Many people think choosing a large high-frequency PCB manufacturer solves everything, but reality is far more complicated. Data rates on a GPON PCB regularly hit several Gbps, and the optical module is neurotically sensitive to power and clock — even a slight fluctuation in the board shop’s process can cause the entire board to drop packets badly enough to make you question your own competence.

One time we switched to a new high-frequency PCB supplier, and when the prototypes came back and were tested, the optical module’s receive sensitivity had inexplicably dropped by 1.5dB. It took two days to discover that the reference plane underneath the clock trace had been split, forcing the return path to take a large detour, and phase noise shot straight up. You see, a lot of the time the problem is not in the clock chip itself — it is in the PCB’s physical structure. Our clock source’s datasheet specified phase noise at -158dBc/Hz at a 10kHz offset, but once mounted on the board, measured performance degraded to -152dBc/Hz, purely because the routing was not done carefully. After that, I set myself an ironclad rule: the layer directly under a clock trace must always be a complete, uninterrupted analog ground, with at least three trace-widths of clearance on every side to keep any digital signal or power trace away. This approach looks wasteful of board space, but it saves an enormous amount of debugging time.

Another easily overlooked issue is module power supply. Burst reception in optical modules is extremely intolerant of power ripple, especially on the OLT side, where a few millivolts of ripple can cause the decision threshold to drift. I once saw a design that, to save effort, powered both the optical module’s 3.3V and the digital section’s 3.3V from a single shared LDO — and during traffic testing, upstream bursts would occasionally lose their preamble. After separating the power supplies with an independent LDO, adding a ferrite bead, and a two-stage LC filter, the problem disappeared immediately. From then on, when I lay out a GPON PCB, the optical module’s power is always routed separately, even if it means using an extra LDO — it is worth it. And the power trace needs to be wide, branching directly from the power entry point without sharing any copper with the digital circuitry.

Module interface routing on a GPON PCB also has its own nuances. Many people focus only on differential signal length matching and forget that the laser driver line is a current-type signal — the moment parasitic inductance gets even a bit large, the eye diagram collapses along with it. I generally require the trace from the driver end to the optical module pad to stay under 15mm, with a trace width of at least 10mil, and an opening on the back side with thickened copper to minimize loop inductance as much as possible. These details are things a high-frequency PCB manufacturer will not necessarily flag proactively, since they are only responsible for producing whatever the Gerber says — but these design habits are exactly what determines whether your board actually works or just sits there looking useless.

At the end of the day, for a high-speed board like GPON, choosing a high-frequency PCB supplier is only step one. What actually separates good designs from bad ones is your own understanding of clocks, power, and module interfaces. The board shop can help you control impedance, but they cannot decide how current returns or how noise couples for you. These are pitfalls you only truly understand once you have fallen into them.

The longer I have worked in GPON, the more I feel that whether a board runs stably often has nothing to do with the chip — it comes down to the power architecture you chose and the process level of your high-frequency PCB supplier. I had a project where the optical module’s 3.3V supply line, according to the chip datasheet, did not seem to require particularly tight ripple — we used a fairly ordinary LDO, and receive sensitivity kept drifting during testing. It took chasing the issue down with a spectrum analyzer, bit by bit, to discover that switching noise from an upstream DC-DC converter was coupling into the optical module’s supply loop through the ground layer, and that noise frequency happened to fall right inside GPON’s burst-receive sensitive band. The board was only a four-layer design, ground plane integrity was poor, and no amount of adjusting decoupling capacitors could suppress it. This experience made it completely clear to me that power design on a GPON PCB cannot just be about voltage and current — you have to treat the entire board’s return-current path as a high-frequency system, especially when multiple power rails coexist, where a chip vendor’s reference design alone falls far short.

We later switched to a different high-frequency PCB supplier, and they directly recommended changing the stack-up to six layers, dedicating complete planes for power and ground, and routing the BOSA driver circuit’s power supply separately from the digital section’s power supply. After this change, without swapping a single chip, the sensitivity spec stabilized. So my view is: for broadband optical access equipment like GPON, the PCB manufacturer’s RF experience can sometimes matter more than the schematic design itself. Hand a high-frequency board over to a shop that has only ever built ordinary digital boards, and even a slight drift in impedance control or dielectric constant deviation will close GPON’s SerDes eye diagram — especially on upstream bursts, where timing margin is already thin.

One more thing — the ringing on the I2C bus’s SDA and SCL lines. Many hardware engineers instinctively add TVS diodes, thinking that guarantees safety, but the TVS’s junction capacitance can pull down the signal slew rate enough that the BMC SoC fails to recognize the correct start bit, and packet loss climbs while software and hardware end up blaming each other. The most absurd case I ever hit was caused by a missing grounding spring clip on the optical module’s metal housing, which let common-mode interference land directly on the I2C line — and it took forever to figure out why. All these messy issues ultimately point to one fact: a GPON board looks simple, but inside it, high-frequency, analog, power, and digital signals are all tangled together. If the high-frequency PCB supplier you choose has no experience with optical communication boards, whatever they produce is likely to fail during certification or mass production.

After several years in this field, I have increasingly come to believe that a board’s fate is largely decided the moment you select a high frequency PCB manufacturer. I used to think circuit design was the real test of skill; reality taught me otherwise — GPON PCB board material selection and manufacturing precision directly determine whether all those carefully designed burst-mode circuits will actually function. Take the simplest example: the OLT’s tolerance window for upstream burst signals is that narrow — if the board’s dielectric constant consistency is poor and transmission delay drifts around, how is the OLT supposed to accurately capture the preamble? That is not something an algorithm alone can fully compensate for.

I have dealt with plenty of high frequency PCB suppliers, but genuinely few actually understand optical communication requirements. Many suppliers lump communication boards together with ordinary digital boards, delivering the same FR-4 grade and calling ±10% impedance control good enough. In GPON, when the laser driver signal’s few-nanosecond rising edge reflects off an impedance discontinuity and superimposes onto the burst-enable signal, it produces an extra glitch right as the laser turns on — invisible on the eye diagram, but it raises the noise floor during neighboring ONUs’ burst windows, and in severe cases it disrupts other ONUs’ synchronization entirely. I eventually bit the bullet and switched to a supplier focused specifically on high-frequency board material — nearly double the cost, but impedance control held to ±5%, and gold-finger plating thickness uniformity was noticeably better, immediately cleaning up the upstream eye diagram.

On the laser side, many people carry over the design mentality from continuous-mode optical modules, thinking that as long as it lights up, it works. GPON’s burst mode is nowhere near “as long as it lights up” — it requires the laser to go from fully off to stable emission within a few microseconds, with optical power and extinction ratio hitting spec instantly. The establishment time for the bias circuit and modulation current in between needs to work together with the APC loop to dynamically adjust. One pitfall I hit was assuming the monitor photodiode’s response delay was too idealized, which caused the APC to keep swinging current back and forth during the first several dozen bits of a burst — the extinction ratio on the first few bits was unusable and the OLT threw errors immediately. We later modified the feedback loop compensation and added a pre-charge treatment on the driver chip’s burst-enable pin, which finally compressed establishment time within spec.

There is another easily overlooked detail — how the PCB’s thermal design affects the laser’s burst characteristics. ONU modules are compact, and a DFB laser’s junction temperature fluctuates periodically under burst mode; if the PCB’s copper area is insufficient, heat accumulation causes the laser’s wavelength to drift slowly, which becomes especially noticeable during high/low temperature testing. I later required the high frequency PCB manufacturer to add stepped copper under the laser pad and increase the surface copper thickness to 2oz, which noticeably narrowed the temperature rise range — burst after burst, temperature fluctuation was cut in half and wavelength stability improved considerably. None of this happens unless you push and grind through it repeatedly with the supplier — they will not proactively help you think it through.

So when I talk with newcomers now, I always say the same thing: GPON hardware design is a systems-level undertaking, not something you finish by drawing a schematic and routing a few differential lines. Whether the high frequency PCB supplier you choose understands optical communication directly determines whether you will spend the next three months chasing down hard-to-diagnose problems on your board.